Data Rate; Data Assembly/Transfer - Control Data Corporation INFORMATION SYSTEMS TERMINAL II Hardware Maintenance Manual

The data following the Start bit is assembled and passed on
to the microprocessor as a logical 1 if it has the same
polarity as the Start bit; otherwise, it is assemblec and
passed on as a logical O.
Word Parity - The receive logic does not have parity check
circuits. Received word parity checking is accomplished by
the terminal controlware program.
Data Rate - The receiver nominal data rate is 1200 bps.
When measured at the receiver inputs, the combination of
frequency differential between receiver and transmitter,
plus network distortion should not make the data string:
• Have the rising and falling edges more than 40 per-
cent away from the 1200 bps nominal positioning.
This 40 percent applies to any edge of any bit
within the 21-bit word. Timing is resynchronized
upon detection of the next Start bit, so the error
is noncumulative.
• Contain bit times whose levels are stretched or
shortened by more than 40 percent of the nominal
833-microsecond bit duration (1167- to 500-
microsecond duration) .
Data Assembly/Transfer - Upon detection of the Start bit,
the receiver logic starts clocking the incoming serial data
into a 7-bit shift register. When the register is full,
its contents are parallel-transferred to a holding register
and the communication ready status/interrupt set. The
shift register is available to receive the next 7 bits.
The data in the holding register must be removed before the
second byte of 7 bits is received to avoid losing data.
The time available between the communication ready and the
lost data condition is:
7 bits at 0.833 millisecond/bit
=
5.83 milliseconds
The second assembled byte loads into the holding register
and the process repeats for the last 7 bits of the 21-bit
word.
Figure 4-4 shows the 21-bit incoming serial word and the
way it passes on to the processor in 3 bytes.
82100083
\
4-7