Control Data Corporation INFORMATION SYSTEMS TERMINAL II Hardware Maintenance Manual page 84

Timing
Figures 4-13, 4-14, and 4-15 show the three possible cases
of interface timing for input and output cycles. The
processor in the three cases starts the sequence in the
same fashion1 the difference between cases depends exclu-
sively on the device response. All timing is referenced to
the parallel channel connector RJ2 at the terminal.
The three cases described for the output cycle (no extra
wait states, extra wait states, and timeout) also apply to
the input instruction, the only difference in requirements
being that in input cycles the device must have the
requested data on the bus before 750 nanoseconds for the no
extra wait state case or before the external ready goes
high for the extra wait states case.
Output Cycle - The processor places the address and data on
the bus (shown by the drivers going from tristate floating
to bipolar state). Fifty nanoseconds later the External
Write goes active (low). At this time, the devices on the
bus can start sampling the address code, and the device
that matches it can start conditioning the external ready
line.
The External Output signal goes active (low) 250 nano-
seconds after the External Write. The data is perfectly
stable at this time, and the addressed device can use this
strobe to latch the data. The processor timing stops and
the sequence is restarted by the External Ready Signal.
The processor samples the external ready line continuously,
starting 750 nanoseconds after the External Write was
issued. To allow for gate delays, cable length, and a
safety margin, the device should condition the external
ready line within 625 nanoseconds after the External Write
is received. It should be in the high state (ready) if the
data on the data bus was taken or processed1 pulled down
(not ready) otherwise.
• Output with no extra wait states (figure 4-13) - If
the external ready line is high and stable 750 nano-
seconds after the External Write, the processor
assumes that the data was successfully transferred
and terminates the output cycle by turning all the-
drivers off and executing the next program
instruction.
4-22 82100083