Control Data Corporation INFORMATION SYSTEMS TERMINAL II Hardware Maintenance Manual page 78

Program Instructions
The processor can, by means of I/O instructions, transfer
information between itself and the serial channel interface
as summarized in table 4-2 and discussed in the following
paragraphs.
TABLE 4-2. SERIAL CHANNEL I/O INSTRUCTIONS
N~E
ADDRESS DESCRIPTION
Load Serial Data Output 06 Data to be transmitted
Load Serial Control Output 07
Control parameters
Read Serial Data Input
05
Data received
Read Serial Status
Input 06 Status information
Load Serial Data (Output 06) - Upon reception of this func-
tion, the module transfers the contents of the data bus
into the serial transmitter. If the transmitter is condi-
tioned to transmit less than 8 data bits, it discards the
excess most significant bits of the 8-bit-wide data bus;
that is, the data bits to be transmitted have to be
right-justified.
Before trying this command, the processor, or the system,
must ensure the character-request signal is active (the
transmit-holding register is empty); otherwise, data may be
lost.
Upon loading of a character, the module activates the RTS
signal and waits until the CTS becomes active before
clocking the serial data out.
The module generates the Start, Parity, and Stop bits
(according to the features previously selected) and inserts
them in the corresponding bit slots.
Load Serial Control (Output 07) - The module loads the con-
tents of the data bus into the control register. The
information of the data bus is interpreted as follows:
• Data Bus Line 0 (Enable CREQ Interrupt) - If this··
line is a 1, it enables the character request inter-
rupt; if a 0, it disables it. An interrupt is
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