Control Data Corporation INFORMATION SYSTEMS TERMINAL II Hardware Maintenance Manual page 85

• Output with extra wait states (figure 4-14) - If the
external ready line is low 750 nanoseconds after the
External Write, the processor goes into Wait
m~de
until it sees the external ready line go high. At
this point, the sequence continues as described in
the previous paragraph. Notice that in the Wait
mode the processor could not execute the program;
therefore, the processor overall throughput is
decreased.
• Output with timeout (figure 4-15) - If the external
ready line is low 750 nanoseconds after the External
Write and remains low for the next 64 microseconds
(+20 percent), the interface terminates the output
cycle by simulating an External Ready and setting a
timeout status bit. Note that:
The timeout condition is guaranteed not to occur
if the external ready line is high and stable
within 43.2 microseconds after the External Write
signal.
Since the processor does not know whether the
completion of the cycle was due to a device-
activated External Ready or a timeout condition,
the driver routine for this interface should have
a check of the status bit immediately after the
output instruction.
While in the Wait mode, the processor is not
refreshing the program memory. The processor
must perform 128 refresh cycles during every
2-millisecond period in order to maintain the
program memory contents. These refresh cycles
are performed automatically by the processor, one
after each fetch instruction operation. Given
the worst case practical condition of executing
block move instructions located in the display
memory space with all memory references also
within the display memory space, there is 752
microseconds to spare during any 2-millisecond
period while still satisfying the refresh
requirements. To ensure that program memory
refresh requirements are met under all condi-
tions, the program prevents the occurrence of
more than 11 timeout conditions during any
2-millisecond period.
The timeout status is automatically reset at the
beginning of an I/O cycle.
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