IBM 7012 G Series Service Manual page 38

Enabling at least one processor from the STAND-BY MENU
There are other resident PON tests to check other system resources. These tests are a
subset of the SystemGuard maintenance offline tests, and reside within the flash EEPROM.
These tests are divided into the following groups:
BUMP Quick I/O Test Group
JTAG (Joint Tests Action Group) Test Group
Direct I/O Test Group These tests check the accessibility of the Standard and Direct I/O
CPU Test Group
DCB (Data CrossBar) and Memory Test Group
Interrupt Test Group
MCA Test Group
CPU Multiprocessor Test Group
2
I C Bus Test Group
The following is an example of the output when running these PON tests:
.. Bump [01.01.00] DEBUG LINE TEST
.. Bump [01.02.00] S1 ASL (BUMP) TEST
.. Bump [01.03.01] S2 ASL (REM.) TEST
.. Bump [01.04.00] S3 ASL (SPE.) TEST
.. Bump [01.05.00] FLASH EP. CONTENT TEST
.. Bump [01.06.00] NVRAM CONTENT TEST
.. Bump [01.07.00] EPROM CONTENT TEST
.. Bump [01.08.00] TOD TEST
.. Bump [01.09.00] FLOPPY–D CNT. TEST
.. Bump [01.10.00] BPP REGISTERS TEST
.. Bump [01.11.00] MISC. REGS TEST
.. Bump [06.05.00] TOD–BUMP IT TEST
Note that the PON test can be suppressed if the fast IPL flag is enabled through
SystemGuard.
2-8
Service Guide
These tests check the accessibility and the functions of the
standard and direct I/O components from the BUMP: Async lines
(S1, S2, and S3), EEPROMs, NVRAM, Flash EEPROM, and TOD
(Time-Of-Day).
These tests check the chip-to-chip connections using the JTAG
features.
components from the CPUs: IONIAN, NVRAM access, EPROM
access, TOD, and the diskette.
These tests are performed by all of the processors and check the
status of the CPU cards: processor, address translation, L1 and L2
caches.
These tests check the status of the system planar and memory
cards: data/address lines accessibility, memory components, ECC,
memory refresh (CPU checkstop).
These tests collectively check the interrupt system: BUMP-CPU,
CPU-CPU (CPU checkstop).
Not applicable
These tests check the multiprocessor mechanisms, atomic
instructions, cache coherency, main memory sharing, and
multi-resources sharing.
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* PON TESTS *
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OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK