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SRCL (Shift Register Recirculate Input)
Generated on LSI chip ME16 pin 38. A high SRCL signal along with
a single CLKTB2 pulse is generated at the end of each PRIME interval.
This clocks a dummy character into the shift register.
ID
(Light Detect)
Generated on LSI chip ME16 pin 17. Signal LD is normally high
indicating no error in the video circuit.
However, if the print head
travels from the left limit switch (RTPSW) to the right limit switch
(EOPSW) with no STROBE pulse generated by the timing fence, then a latch
is set within the chip causing LD to go low. This indicates an error
condition. The internal LD latch can be reset only be de-selecting the printer.
PRIME (Prime)
Generated on LSI chip ME16 pin 37.
PRIME goes active high for
100-500 milliseconds during a Power Prime (PWRPRM) and approximately
100-400 microseconds during any of the following conditions:
(1) A low DCPRM input from LSI chip ME25,
(2) The printer has just been selected (a low SLCT input to LSI
chip ME16) and the Delete Inhibit (DELINH) option is not used
(jumper E14 to E15 is not connected),
(3) A line of data has just been printed (CIPX out of LSI chip ME16
has just gone high).
Prime initializes the printer logic, resets the shift register and
loads a dummy character.
CSBSY (Cause Busy)
Generated on LSI chip ME16 pin 35. CSBSY goes active low when a
dummy character (TB8) is detected at the shift register output and a Prime
operation is not in progress. This condition indicates that the 80th char-
acter has just been loaded into the shift register (without a carriage re-
turn code). The low CSBSY signal then generates a low BUSY output from
LSI chip ME25.
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