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4.5 SHIFT REGISTER (BUFFER)
The printer storage buffer consists of two quad 81-bit shift register
MOS elements (ME18 and ME19). These elements provide an 8 x 81-bit storage
capacity or one full line of 80 characters. The extra character storage
(i.e., 81 instead of 80) is used for storing a dummy character (a ONE in
bit 8). Detection of this dummy character at the shift register output
indicates that the 80th character for that line has just been shifted into
memory.
A high PRIME input to ME18 and ME19, disables all other inputs and
asynchronously resets the entire register. When PRIME is low, the shift
register operates in either the normal or the recirculate mode. With the
Recirculate input (SRCL) low, each CLKTB1 or CLKTB2 pulse clocks the DS1-
DS8 inputs into the shift register. With SRCL high, the register is in
the recirculate mode. The first three stages in each shift register element
are recirculated internally. The fourth stage in ME19 is recirculated by
the external connection of TB4 to the Recirculate Input (R.I.). The R.I.
terminal for the fourth stage in ME18, however, is tied to +5V. As a re-
sult, when the SRCL input is high, CLKTB recirculates the TB1-TB7 outputs
back to the inputs and forces a ONE into the eighth stage (TB8).
The actual shift register timing depends on which of the following
printer operations is taking place: 1) a prime condition; 2) data re-
ception 3) reception of a carriage return code (octal 015) prior to the
80th character in a line; or 4)
~rinting
a line of characters.
(I) Priming the Shift Register
During a prime condition, LSI element ME16 generates a high
PRIME signal. While PRIME is high, all shift register stages
are automatically reset, independent of the data inputs.
After PRIME goes low, SRCL remains high and a single CLKTB1
pulse is generated. At this time, a ONE is clocked into bit 8
(due to +5V at the recirculate input ME18 pin 15), generating
a dummy character at that location.
4-12
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