Table of Contents
Advertisement
4-3 PLL CIRCUITS
4-3-1 VCO CIRCUIT
The VCO circuit (Q4, Q5, D3, D4) directly generates both of the
1st LO frequency for receiving (134.35–141.575 MHz) and the
transmit frequency (156.025–157.425 MHz).
While receiving, the VCO output signal (1st LO signal) is am-
plifi ed at the buffer amplifi ers (Q6, Q7) and passed through
the TX/RX switch (D8), then applied to the 1st mixer (Q22).
While transmitting, the VCO output signal (transmit signal)
is amplified at the buffer amplifiers (Q6, Q7) and passed
through the TX/RX switch (D7), then applied to the pre-driver
(Q10).
A portion of the VCO output signal from the buffer amplifi er
(Q6) is fed back to the PLL IC (IC1, pin 2) as the comparison
signal via the buffer amplifier (Q3) and the LPF (L2, C34,
C35).
4-3-2 PLL CIRCUIT
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio of the programmable divider.
The buffer amplifi ed signals are applied to the PLL IC (IC1,
pin 2) via the LPF (L2, C34, C35). The applied signals are
divided at the prescaler and programmable counter section
according to the "PDATA" from the CPU (LOGIC BOARD; IC1
pin 8). The divided signal is phase-compared with the reference
frequency at the phase detector.
The phase difference is output from pin 8 as a pulse type
signal after being passed through the charge pump section.
The output signal is passed through the loop fi lter (R7–R9,
R41, C4, C5, C43, C44) to be converted into the DC voltage,
and is then applied to the VCO circuits as the lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
• PLL CIRCUITS
UNLK
3
PSTB
4
PCK
5
PDATA
15
X1
16
to the FM IF IC (IC2, pin 2)
S5V
7
Programmable
DATA interface
Reference
Phase
counter
detector
17
4-4 DSC CIRCUITS
• DECODING
A portion of the demodulated AF signals from the FM IF IC
(IC2, pin 9) are passed through the LPF (Q38) to fi lter DSC
signal. The filtered DSC signal is applied to the DSC de-
coder (IC15, pin 2). The decoded DSC signal is output from
pin7, and then applied to the CPU (LOGIC BOARD; IC1, pin
14). Then the CPU controls the transceiver according to the
DSC content.
• ENCODING
The DSC signals (FSK) are generated by the CPU (LOGIC
BOARD; IC1) and output from pins 141. The DSC signals
are applied to the buffer amplifi er (LOGIC BOARD; IC5,
pin 3). The buffer amplifi ed DSC signals are output from
pin 1, and passed through the LPF (IC8, pins 5, 7), and
applied to the modulation circuit (D2) via the deviation
adjustment pot (R327) to modulate the VCO oscillating
signal.
4-5 PUBLIC ADDRESS (PA) CIRCUIT
The Public Address (PA) circuit power amplifies the audio
signals from the microphone. The power amplifi ed MIC sig-
nals are output to the connected external speaker or hailer.
The MIC signals from the microphone (HM-150B/SW or
optional HM-157) are passed through the AF mute circuit
(IC5, pins 10, 11), and applied to the microphone amplifier
(IC8, pin 2). The amplified MIC signals are output from pin 1,
and applied to the electric volume controller (IC13, pin 1) via
the AF mute circuit (IC5, pins 8, 9). The volume controlled
MIC signals are then passed through the AF mute circuit
(Q65), and applied to the AF power amplifier (IC14, pin 1) to
be amplified to obtain 5 W (min.) of AF output power.
The power amplifi ed AF signals are output from pin 4, and
applied to the connected external speaker or hailer.
LPF
2
Prescaler
IC1
µPD3140GS
counter
8
Loop
Charge
pump
filter
4 - 3
Buffer
Buffer
Q7
Q3
Buffer
Q6
VCO
Q4, Q5, D3, D4
to the TX/RX switch (D7, D8)
Hide quick links:
Advertisement
Table of Contents
