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Lake Shore Model 330 Autotuning Temperature Controller User's Manual
If the Service Request is enabled, setting any of these bits causes the Model 330 to pull the SRQ
management low to signal the BUS CONTROLLER. These bits reset to zero upon a serial poll of the Status
Byte Register. Inhibit or enable these reports by turning their corresponding bits off or on in the Service
Request Enable Register. The QSRE command sets the bits. Setting a bit in the Service Request Enable
Register, enables that function. See the QSRE command.
Service Request (SRQ) Bit (6) – Determines whether the Model 330 reports via the SRQ line. Four bits
determine which status reports to make. If bits 0, 1, 2, 4 or 5 are set, then the corresponding bit in the Status
Byte Register is set. The Model 330 produces a service request only if bit 6 of the Service Request Enable
Register is set. If disabled, the BUS CONTROLLER still examines Status Byte Register status reports by serial
poll (SPE), but the Service Request cannot interrupt the BUS CONTROLLER. The QSTB common command
reads the Status Byte Register but will not clear the bits. Certain bits in the Status Byte Register continually
change.
The Standard Event Status Bit and the Status Reports for the Overload, Display Data Ready, and Control Data
Ready continuously update to reflect current controller status. The Control Channel Limit is latched (set to 1)
and remains latched until the Status Byte Register is read. See below for Status Byte Register bit
assignments. These reports occur only if enabled in the Service Request Enable Register.
Sample Data Ready (SDR) Bit (0) – When set, a valid sample reading is available.
Control Data Ready (CDR) Bit (1) – When set, a valid control data reading is available.
Control Limit Ready (CLE) Bit (2) – When set, indicates the control sensor reading is inside the chosen limit
from the setpoint. The bit will not revert to zero if the reading falls back outside the chosen limit. If this report is
read and the control sensor reading is still inside the limit, the Model 330 sets the CLE bit again. Enter the
control channel limit with the CLIM device dependent command.
Overload Indicator (OVI) Bit (4) – When set, indicates a display overload on any selected channel. Issues a
Service Request if enabled.
Standard Event Status (ESB) Bit (5) – When set, indicates if one of the bits from the Standard Event Status
Register has been set. (See Paragraph 4.1.4.2.)
4.1.3.2
Standard Event Status Register and Standard Event Status Enable Register
The Standard Event Status Register supplies various conditions of the Model 330.
Bit –
Weighting –
Bit Name –
Bits 2 and 6 are not used. Reports of this register interrupt the user only if the bits are enabled in the Standard
Event Status Enable Register and if bit 5 of the Service Request Enable Register is set.
The Standard Event Status Enable Register allows the user to enable any of the Standard Event Status
Register reports. The Standard Event Status Enable command (QESE) sets the Standard Event Status Enable
Register bits. Setting a bit of this register, enables that function. To set a bit, send the command QESE with the
sum of the bit weighting for each bit to be set. See the QESE command.
The Standard Event Status Enable Query, QESE?, reads the Standard Event Status Enable Register. QESR?
reads the Standard Event Status Register. Once this register has been read, the bits are reset to zero.
Power On (PON) Bit (7) – Set to indicate a controller off-on-off transition.
Command Error (CME) Bit (5) – Set to indicate a command error since the last reading. Controller unable to
interpret a command due to syntax error, unrecognized header or terminators, or unsupported command.
Execution Error (EXE) Bit (4) – Set to indicate an execution error. Occurs when the controller is given a task
outside its capabilities.
Remote Operation
STANDARD EVENT STATUS REGISTER FORMAT
7
6
5
128
64
32
PON
Not Used
CME
4
3
2
16
8
4
EXE
DDE
QYE
1
0
2
1
Not Used
OPC
4-3
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