Processor Memory Map; Table 7-2. Suggested Chrp Memory Map - Emerson MVME51005E Installation And Use Manual

Processor Memory Map

The following table describes a suggested CHRP Memory Map from the point of view of the
processor. This memory map is an alternative to the PREP memory map. Note: in all
recommended CHRP maps, the beginning of PCI Memory Space is determined by the end of
DRAM rounded up to the nearest 256MB-boundry as required by CHRP. For example, if
memory was 1G on the baseboard and 192MB on a mezzanine, the beginning of PCI memory
would be rounded up to address 0x50000000 (1G + 256M).

Table 7-2. Suggested CHRP Memory Map

Processor Address
Start
0000 0000 top_dram
top_dram 8000 0000
8100 0000 9FFF FFFF
A000 0000 A1FF FFFF
AFFF 0000 AFFF FFFF
F400 0000 F7FF FFFF
F800 0000 FBFF FFFF
FC00 0000 FDFF FFFF
FE00 0000 FE7F FFFF
FE80 0000 FEF7 FFFF
FEF8 0000 FEF8 FFFF
FEF9 0000 FEFE FFFF
FEFF 0000 FEFF FFFF
FF00 0000 FF7F FFFF
FF80 0000 FF8F FFFF
FF90 0000 FFEF FFFF
FFF0 0000 FFFF FFFF
Notes
1. Programmable via Hawk ASIC.
2. The actual Power Plus II size of each ROM/FLASH bank may vary.
3. The first 1MB of ROM/FLASH Bank A appears at this range after a reset if the
rom_b_rv control bit is cleared. If the rom_b_rv control bit is set, this address maps to
ROM/FLASH Bank B.
Size
End
dram_size
variable
512MB
32MB
64KB
64MB
64MB
32MB
8MB
7.5MB
64KB
384KB
64KB
8MB
1MB
6MB
1MB
MVME51005E Single Board Computer Installation and Use (6806800A38B)
7 Programming the MVME5100
Definition
System Memory (onboard DRAM)
PCI Memory Space
A32/D32 space mapped to VMEbus
starting address of 0100 0000
A24/D16 space mapped to VMEbus
starting address of F000 0000
A16/D16 space mapped to VMEbus
starting address of FFFF 0000
FLASH Bank A (optional)
FLASH Bank B (optional)
Reserved
PCI/ISA I/O Space
Reserved
System Memory Controller
Registers
Reserved
Processor Host Bridge Registers
FLASH Bank A (preferred)
FLASH Bank B (preferred)
Reserved
Boot ROM
Notes
1
1, 5
1, 2
1, 2
1
4
1, 2
1, 2
3
75