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Emerson MVME3100 Series Programmer's Reference Manual

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MVME3100 Single Board Computer
Programmer's Reference
6806800G37A
April 2008

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Summary of Contents for Emerson MVME3100 Series

  • Page 1 MVME3100 Single Board Computer Programmer’s Reference 6806800G37A April 2008...
  • Page 2 Emerson reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Emerson to notify any person of such revision or changes.

  • Page 3: Table Of Contents

    2.10 Flash Memory ............. . 40 MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 4 2.15 MPC8540 LBC Clock Divisor ..........44 A.1 Emerson Network Power - Embedded Computing Documents ......45 A.2 Manufacturers’...

  • Page 5: List Of Figures

    Block Diagram ............16 MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 6 List of Figures MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 7 MVME3100 Features Summary ........
  • Page 8 List of Tables MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 9: About This Manual

    MPC8540 interrupt controller, Flash memory, two-wire serial interface addressing, and other device and system considerations. Appendix A, Related Documentation, provides a listing of related Emerson manuals, vendor documentation, and industry specifications. MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 10 Programmable Interrupt Controller PCI Mezzanine Card Input/Output Module Programmable Logic Device PCI Mezzanine Card (IEEE P1386.1) Power-On Reset PReP PowerPC Reference Platform PrPMC Processor PMC QUART Quad Universal Asynchronous Receiver/Transmitter Read/Write Random Access Memory MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 11 Used to characterize user input and to separate it Courier + Bold from system output Reference Used for references and for table and figure descriptions File > Exit Notation for selecting a submenu <text> Notation for variables and keys MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 12 No danger encountered. Pay attention to important information Summary of Changes This manual has been revised and replaces all prior editions. Part Number Publication Date Description V3100A/PG1 First edition 6806800G37A April 2008 Updated to Emerson style. MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 13 > Contact Us > Online Form In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part number, and revision of the manual and tell us how you used it. MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 14 About this Manual MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 15: Board Description And Memory Maps

    The MVME3100 Single-Board Computer Programmer’s Reference provides general programming information, including memory maps, interrupts, and register data for the MVME3100 family of boards. This document should be used by anyone who wants general, as well as technical information about the MVME3100 products.

  • Page 16: Table 1-1 Mvme3100 Features Summary

    Board Description and Memory Maps Overview Figure 1-1 shows a block diagram of the MVME3100 and Table 1-1 lists the features of the MVME3100. Figure 1-1 Block Diagram Front Panel RST/ABORT GigE COM1 PMC 1 Front IO PMC 2 Front IO...
  • Page 17 P0 I/O. The other two channels are not used. Ethernet – Two 10/100/1000 MPC8540 Ethernet channels for front-panel I/O and rear P2 I/O – One 10/100 MPC8540 Ethernet channel for rear P2 I/O MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 18: Table 1-2 Mvme712-101 Rtm Features Summary

    – Two RJ-45 connectors with integrated LEDs for rear panel I/O: one 10/100/1000 Ethernet channel and one 10/100 Ethernet channel – One PIM site with rear-panel I/O Miscellaneous – Four rear-panel status indicators: 10/100/1000 and 10/100 Ethernet link/speed and activity LEDs MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 19: Memory Maps

    E10F FFFF MPC8540 CCSR E1100 0000 E1FF FFFF 15MB Not Used E200 0000 E2FF FFFF 16MB Status/Control Registers/UARTs, External Timers E300 0000 EFFF FFFF 208MB Not Used F000 0000 F7FF FFFF 128MB Reserved MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 20: Vme Memory Map

    After RESET, the MPC8540 does not map any PCI memory space (inbound or outbound), and does not respond to Config cycles. 1.3.3 VME Memory Map The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2GB. 1.3.4 System I/O Memory Map...
  • Page 21 External PLD Tick Timer 4 Compare Register E202 0048 External PLD Tick Timer 4 Counter Register E202 004C - Reserved E2FF FFFF 1. Reserved for future implementation 2. 32-bit write only 3. Byte read/write capable MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 22: System Status Register

    Board Description and Memory Maps System Status Register 1.3.5 System Status Register The MVME3100 board System Status register is a read-only register used to provide board status information. Table 1-6 System Status Register System Status Register – 0xE2000000 FIELD OPER...

  • Page 23: System Indicator Register

    1.3.7 System Indicator Register The MVME3100 board provides a System Indicator register that may be read by the system software to determine the state of the on-board status indicator LEDs or written to by system software to illuminate the corresponding on-board LEDs.

  • Page 24: Flash Control/Status Register

    RSVD: Reserved for future implementation. 1.3.8 Flash Control/Status Register The MVME3100 provides software-controlled bank write protect and map select functions as well as boot block select, bank write protect, and activity status for the Flash. Table 1-9 Flash Control/Status Register...

  • Page 25: Pci Bus Status Registers

    PCI_A_64B: PCI bus A 64-bit. A set condition indicates that bus A is enabled to operate in 64- bit mode. A cleared condition indicates 32-bit mode. RSVD: Reserved for future implementation. Table 1-11 PCI Bus B Status Register PCI Bus B Status Register - 0xE2000005 FIELD OPER MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 26: Table 1-12 Pci Bus C Status Register

    3.3V_VIO: 3.3V VIO enabled. This bit set indicates that the PMC bus (PCI bus B) is configured to 3.3V VIO. Table 1-12 PCI Bus C Status Register PCI Bus C Status Register - 0xE2000006 FIELD OPER RESET MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 27: Interrupt Detect Register

    RSVD: Reserved for future implementation. 1.3.10 Interrupt Detect Register The MVME3100 provides an Interrupt Detect register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt. Table 1-13 Interrupt Detect Register...

  • Page 28: Presence Detect Register

    RSVD: Reserved for future implementation. 1.3.12 PLD Revision Register The MVME3100 provides a PLD Revision register that may be read by the system software to determine the current revision of the timers/registers PLD. Table 1-15 PLD Revision Register PLD Revision Register - 0xE2000009...

  • Page 29: Pld Data Code Register

    PLD Data Code Register Board Description and Memory Maps 1.3.13 PLD Data Code Register The MVME3100 PLD provides a 32-bit register that contains the build date code of the timers/registers PLD. Table 1-16 PLD Data Code Register PLD Data Code Register - 0xE200000C...

  • Page 30: External Timer Registers

    1.3.16 External Timer Registers The MVME3100 provides a set of tick timer registers for access to the four external timers implemented in the timers/registers PLD. These registers are 32-bit registers and are not byte writable. The following sections describe the external timer prescaler and control registers.

  • Page 31: 1.3.16.3 Compare Registers

    If the clear-on-compare mode is enabled, the counter is also cleared. For periodic interrupts, this equation should be used to calculate the compare register value for a specific period (T): Compare register value = T (us) MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 32: 1.3.16.4 Counter Registers

    Geographical Address Register The VMEbus Status register in the TSi148 provides the VMEbus geographical address of the MVME3100. This register reflects the inverted states of the geographical address pins at the 5- row, 160-pin P1 connector. MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 33: Programming Details

    MPC8540 LBC Clock Divisor on page 44 MPC8540 Reset Configuration The MVME3100 supports the power-on reset (POR) pin sampling method for MPC8540 reset configuration. The states of the various configuration pins on the MPC8540 are sampled when reset is de-asserted to determine the desired operating modes. The following table describes the configuration options and the corresponding default setting.
  • Page 34 32-bit ROM TSEC2_ Resistor TSEC2 Protocol TSEC2 controller uses TXD7 Configuration GMII protocol (or RGMII if TSEC2 configured in reduced mode) TSEC2 controller uses TBI protocol (or RTBI if TSEC2 configured in reduced mode) MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 35 Configuration 0 added buffer delays 3 added buffer delays 2 added buffer delays PCI-X Output Hold 3 added buffer delays Configuration 2 added buffer delays 1 added buffer delay 0 added buffer delays MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 36 Debug info from the DDR SDRAM controller is driven on MSRCID & MDVAL pins MSRCID1 Resistor DDR Debug Debug info on ECC pins Configuration instead of normal ECC ECC pins function in normal mode MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 37: Mpc8540 Interrupt Controller

    8. ECC signals from memory devices must be disconnected. MPC8540 Interrupt Controller The MVME3100 uses the MPC8540 integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.

  • Page 38: Local Bus Controller Chip Select Assignments

    3. 32-bit timer registers are byte readable, but must be written as 32 bits. Two-Wire Serial Interface A two-wire serial interface for the MVME3100 is provided by an I C compatible serial controller integrated into the MPC8540. The MPC8540 I...

  • Page 39: User Configuration Eeprom

    3. The device address is user selectable using switches on the RTM. The recommended address setting for the MVME3100 is $AA. User Configuration EEPROM The MVME3100 board provides two 64KB dual address serial EEPROMs for a total of 128KB user configuration storage. These EEPROMs are hardwired to have device IDs as shown in Table 2-4 on page 38, and each device ID will not be used for any other function.

  • Page 40: Ethernet Phy Address

    Software must program one or two LBC chip selects based on the VPD Flash packet information. The following table defines the supported Flash density options for each bank. The factory configuration for the MVME3100-1152 is one bank of 64MB; for the MVME3100-1263, it is one bank of 128MB.

  • Page 41: Pci Idsel Definition

    PCI IDSEL Definition Programming Details The MVME3100 provides a dual boot option for booting from one of two separate boot images in the boot Flash bank, which are referred to as boot block A and boot block B. Boot blocks A and B are each 1MB in size and are located at the top (highest address) 2 MB of the boot Flash memory space.

  • Page 42: Pci Arbitration Assignments

    PCI Arbitration Assignments The integrated PCI/X arbiters internal to the MPC8540 and the PCI6520 bridges provide PCI arbitration for the MVME3100. The MPC8540 provides arbitration support for itself and the four PCI-X devices on PCI bus A. The PCI6520 secondary PCI/X interface arbiters support external bus masters in addition to the PCI6520.

  • Page 43: Clock Distribution

    Clock Distribution Programming Details The arbitration assignments on the MVME3100 are shown in the follow table so that software may set arbiter priority assignments if necessary. Table 2-9 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master(s) MPC8540 PCI_REQ/GNT[0] sATA Controller...

  • Page 44: Mpc8540 Real-Time Clock Input

    (LCRR[CLKDIV]). For proper operation of the local bus, CLKDIV must be set for divide by 8, which is the default value. The software must leave this register configured for divide by 8 during initialization. MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 45: Emerson Network Power - Embedded Computing Documents

    Documents The Emerson Network Power - Embedded Computing publications listed below are referenced in this manual. You can obtain electronic copies of Emerson Network Power - Embedded Computing publications by contacting your local Emerson sales office. For documentation of final released (GA) products, you can also visit the following website: http://www.emersonnetworkpowerembeddedcomputing.com...
  • Page 46 48720 Kato Road Fremont, CA 94538 Web Site: http://www.exar.com 2-Wire Serial EEPROM Datasheet AT24C512 Atmel Corporation San Jose, CA Web Site: http://www.atmel.com/atmel/support/ Maxim DS1621Digital Thermometer and Thermostat DS1621 Maxim Integrated Products Web Site: http://www.maxim-ic.com MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

  • Page 47: Related Specifications

    P1386 Draft 2.0 and Electronics Engineers, Inc. IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. USB http://www.usb.org/developers/docs/ Universal Serial Bus Specification Revision 2.0 April 27, 2000 MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
  • Page 48 Related Documentation Related Specifications MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)

This manual is also suitable for:

Mvme3100-1152Mvme3100-1263Mvme721-101

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