Programming The Mvme5100; Introduction; Memory Maps; Processor Bus Memory Map - Emerson MVME51005E Installation And Use Manual

Programming the MVME5100

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Introduction

This chapter provides basic information useful in programming the MVME5100. This includes
a description of memory maps, control and status registers, PCI arbitration, interrupt handling,
sources of reset and big/little-endian issues.
For additional programming information about the MVME5100, refer to the MVME5100-Series
Single Board Computer Programmer's Reference Guide, listed in
Documentation
For programming information about the PMCs, refer to the applicable user's manual furnished
with the PMCs.

Memory Maps

There are multiple buses on the MVME5100 and each bus domain has its own view of the
memory map. The following sections describe the MVME5100 memory organization from the
following three points of view:
❏
❏
❏
Additional, more detailed memory maps can be found in the MVME5100-Series Single Board
Computer Programmer's Reference Guide, listed in

Processor Bus Memory Map

The processor memory map configuration is under the control of the PHB and SMC portions of
the Hawk ASIC. The Hawk adjusts system mapping to suit a given application via
programmable map decoder registers. At system power-up or reset, a default processor
memory map takes over.
.
The mapping of all resources as viewed by the MPU (processor bus memory map)
The mapping of onboard resources as viewed by PCI local bus masters (PCI bus
memory map)
The mapping of onboard resources as viewed by VMEbus masters (VMEbus
memory map)
MVME51005E Single Board Computer Installation and Use (6806800A38B)
Appendix D, Related
Appendix D, Related Documentation.
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