Output Signals; Default Operation And Jumper Selection Settings - Analog Devices AD9643 User Manual

UG-293
When connecting the analog input source, use of a multipole,
narrow-band, band-pass filter with 50 Ω terminations is recom-
mended. Analog Devices, Inc., uses TTE and K&L Microwave, Inc.,
band-pass filters. Connect the filters directly to the evaluation
board.
If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.

OUTPUT SIGNALS

The default setup uses the Analog Devices high speed converter
evaluation platform (HSC-ADC-EVALCZ) for data capture. The
output signals from Channel A and Channel B for the AD9643,
AD9613, AD6649, and AD6643
P602, respectively, to the FPGA on the data capture board.
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
This section explains the default and optional settings or
modes allowed on the AD9643/AD9613/AD6649/AD6643
evaluation board.
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P201.
Analog Input
The A and B channel inputs on the evaluation board are set up for a
double balun-coupled analog input with a 50 Ω impedance. This
input network is optimized to support a wide frequency band. See
the AD9643, AD9613, AD6649, and
tional information on the recommended networks for different
input frequency ranges. The nominal input drive level is 10 dBm to
achieve 2 V p-p full scale into 50 Ω. At higher input frequencies,
slightly higher input drive levels are required due to losses in the
front-end network.
Optionally, the Channel A and Channel B inputs on the board
can be configured to use the ADL5202
gain wide bandwidth amplifier. The
included on the evaluation board at U401. However, the path
are routed through P601 and
AD6643 data sheets for addi-
digitally controlled, variable
ADL5202 component is
2V p-p
P S S
A
Figure 3. Default Analog Input Configuration of the
AD9643/AD9613/AD6649/AD6643 User Guide
into and out of the
ways depending on the application; therefore, the parts in the
input and output path are left unpopulated. See the
data sheet for additional information on this device and for
configuring the inputs and outputs. The ADL5202, by default,
is held in power-down mode but can be enabled by adding 1 kΩ
resistors at R427 and R428 to enable Channel A and Channel B,
respectively.
Clock Circuitry
The default clock input circuit that is populated on the AD9643/
AD9613/AD6649/AD6643
transformer-coupled circuit with a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low
amount of jitter to the clock path. The clock input is 50 Ω
terminated and ac-coupled to handle single-ended sine wave
types of inputs. The transformer converts the single-ended
input to a differential signal that is clipped by CR503 before
entering the ADC clock inputs.
The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J506.
A differential LVPECL clock driver output can also be used to
clock the ADC input using the
AD9523 into the clock path, populate R541 and R542 with 0 Ω
resistors and remove C532 and C533 to disconnect the default
clock path inputs. In addition, populate R533 and R534 with
0 Ω resistors, remove R522 and R523 to disconnect the default
clock path outputs, and insert
AD9523 must be configured through the SPI controller software to
set up the PLL and other operation modes. Consult the
data sheet for more information about these and other options.
PDWN
To enable the power-down feature, add a shorting jumper across
P101 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD.
OEB
To disable the digital output pins and place them in a high imped-
ance state, add a shorting jumper across P102 at Pin 1 and Pin 2
to connect the OEB pin to AVDD.
8.2pF
49.9Ω
0.1µF
33Ω
36Ω
P
8.2pF
0.1µF
36Ω
0.1µF
33Ω
49.9Ω
8.2pF
AD9643/AD9613/AD6649/AD6643
Rev. A | Page 4 of 26
ADL5202 can be configured in many different
evaluation board uses a simple
AD9523 (U501). To place the
AD9523 LVPECL Output 2. The
VIN+x
AD9643/AD9613/
AD6649/AD6643
VCM
VIN–x
ADL5202
AD9523