Figure 7-3. Test Formats: Data-Cache Tags; Array Test Data - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
7.4.3

Array Test Data

EDX: Array Pointer
31 30 29 28 27
Way
0 0
EAX: Test Data
31 28 27
0 0 0 0
(E1h) Linear Tag
31
0 0 0 0 0 0 0 0 0
(ECh) Physical Tag

Figure 7-3. Test Formats: Data-Cache Tags

7-10
EAX specifies the test data to be read or written with the
RDMSR or WRMSR instruction (see Figures 7-3 through 7-8).
For example, in Figure 7-3 (top) the array pointer in EDX spec-
ifies a way and set within the data-cache linear tag array (E1h
in bits 7–0 of the array pointer) or the physical tag array (ECh
in bits 7–0 of the array pointer). If the linear tag array (E1h)
were accessed, the data read or written includes the tag and
the status bits. The details of the valid fields in EAX are shown
in Appendix A of the AMD-K5 Processor Software Development
Guide, order# 20007.
19
0 0 0 0 0 0 0 0
23 22
18 13 12
Set 0 0 0 0 0
Valid Bits
Valid Bits
18524C/0—Nov1996
8 7
Array ID
(E1h, ECh)
Test and Debug
0
0
0