AMD K5 Technical Reference Manual page 119

18524C/0—Nov1996
Bus
Arbitration
Address
and
Address
Parity
Cycle
Definition
and
Control
Cache
Control
Figure 5-1. Signal Groups
Signal Overview
AHOLD
BOFF
BREQ
HLDA
HOLD
A20M
A31–A3
AP
ADS
ADSC
APCHK
BE7–BE0
D/C
EWBE
LOCK
M/IO
NA
SCYC
W/R
CACHE
KEN
PCD
PWT
WB/WT
FRCMC IERR TCK
Test and Debug
AMD-K5 Processor Technical Reference Manual
Clock
BF
CLK
(BF1–BF0)
AMD-K5
Processor
TDI TDO TMS
BRDY
BRDYC
Data
D63–D0
and
DP7–DP0
Data
PCHK
Parity
PEN
EADS
HIT
Inquire
HITM
Cycles
INV
FERR
Floating-Point
IGNNE
Errors
BUSCHK
FLUSH
INIT
INTR External
NMI Interrupts,
PRDY Interrupt
Acknowledge,
R/S
RESET and Reset
SMI
SMIACT
STPCLK
TRST
5-3