Test Inputs - Intel UPI- 41A User Manual

Timer Mode
The STRT T instruction connects the internal clock to
the counter input and enables the counter The input
clock is derived from the SYNC signal of the internal
oscillator and the divide-by-32 prescaler The configu-
ration is illustrated in Figure 2-13 Note this instruction
does not clear the timer register Various delays and
timing sequences between 40 msec and 10 24 msec can
easily be generated with a minimum of software timing
loops (at 12 MHz)
Times longer than 10 24 msec can be accurately mea-
sured by accumulating multiple overflows in a register
under software control For time resolution less than 40
msec an external clock can be applied to the TEST 1
counter input (see Event Counter Mode) The mini-
mum time resolution with an external clock is 3 75
msec (267 kHz at 12 MHz)
TEST 1 Event Counter Input
The TEST 1 pin is multifunctional It is automatically
initialized as a test input by a RESET signal and can be
tested using UPI-41A conditional branch instructions
In the second mode of operation illustrated in Figure
2-13 the TEST 1 pin is used as an input to the internal
UPI-41A 41AH 42 42AH USER'S MANUAL
8-bit event counter The Start Counter (STRT CNT)
instruction controls an internal switch which connects
TEST 1 through an edge detector to the 8-bit internal
counter Note that this instruction does not inhibit the
testing of TEST 1 via conditional Jump instructions
In the counter mode the TEST 1 input is sampled once
per instruction cycle After a high level is detected the
next occurrence of a low level at TEST 1 will cause the
counter to increment by one
The event counter functions can be stopped by the Stop
Timer Counter (STOP TCNT) instruction When this
instruction is executed the TEST 1 pin becomes a test
input and functions as previously described

TEST INPUTS

There are two multifunction pins designated as Test
Inputs TEST 0 and TEST 1 In the normal mode of
operation status of each of these lines can be directly
tested using the following conditional Jump instruc-
tions

JT0

JNT0

JT1

JNT1
Figure 2-13 Timer Counter
Jump if TEST 0 1
e
Jump if TEST 0 0
e
Jump if TEST 1 1
e
Jump if TEST 1 0
e
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