TMC TI5VG+ User Manual page 49

Chapter 6 BIOS Configuration
Read Around Write
DRAM optimization feature: If a memory read is addressed to a location
whose latest write is being held in a buffer before being written to
memory, the read is satisfied through the buffer contents, and the read is
not sent to the DRAM. The default setting is Enabled.
Cache Timing
This field sets the timing of the cache in the system. The options are Fast
and Fastest. By default, this field is set to Fast.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
are cached, provided that the cache controller is enabled.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Memory Hole at 15MB Addr.
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to Disabled.
AGP Aperture Size
The field sets aperture size of the graphics. The aperture is a portion of
the PCI memory address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation. The default setting is 64M.
Cyrix M2 ADS# delay
This field is only visible when your system supports a Cyrix M2
processor. It enables or disables the ADS# delay signal for Cyrix M2.
TI5VG+ User's Manual 45