FLIR Tau Camera TAU-0035-00-10 User Manual page 48

4—Tau Digital Data Channel
Note: Figure is not to scale.
CLK
LINE_VALID
CMOS_DATA13 –
CMOS_DATA0
Figure 4-2: CMOS Line Timing (normal clock configuration)
Note: Figure is not to scale.
FRAME_VALID
LINE_VALID
DATA13 – DATA0
4-4
CLK duty cycle is 4/7.
Data may be latched on the rising or falling edge of CLK
95.062 nsec
(10.519 MHz)
t
s_RE
t
s_FE
Pix 0 Pix 1
(13:0) (13:0)
1 / (frame rate)
1 clock
Line 0 Line 1
variable
Figure 4-3: CMOS Frame Timing
June 2011
Tau User's Manual
th
t = 6/7 clock
s_RE
th
t = 3/7 clock
s_FE
Pix 2 Pix
(13:0) (13:0)
n = 79, 159, 319, or 639
Line 2 Line
m = 59, 119, 239, or 479 (NTSC)
or 63, 127, 255, or 511 (PAL)
TAU-0035-00-10, version 150
(idle time)
(idle time)