"Important Alert Items" in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Related Standards Specifications and functions of products covered by this manual comply with the following standards. Standard (Text) No. Name Enacting Organization T10/1365D Rev 10 Working Draft American National American National Standard Information Standards Institute Technology --- SCSI Parallel Interface 4 (ANSI) C141-C015...
REVISION RECORD Date Edition Revised contents published March, 2007 Initial release Specification No.: C141-C015 C141-C015...
PREFACE This manual explains the MBA3073/MBA3147/MBA3300 NP/NC series 3-1/2" intelligent disk drives each having the built-in SCSI controller. This manual details the specifications and functions of the Small Computer System Interface (SCSI) to connect the above listed disk drives to the user system. Also, the manual details various SCSI command specifications and the command processing functions, and provides the information required to creation of host system software.
CONVENTIONS This manual uses the following conventions: NOTE: NOTE indicates the information useful for the user to operate the system. Important information The important information is provided with the "Important" title. The important information text is centered so that the reader can distinguish it from other manual texts. The following gives an example: IMPORTANT The HDD operates as a target (TARG) on the SCSI bus.
Requesting for User's Comments Please use the User's Comment Form attached to the end of this manual to identify user comments including error, inaccurate and misleading information of this manual. Contact to your Fujitsu representative for additional comment forms if required.
MANUAL ORGANIZATION • General Description Product/ • Specifications Maintenance • Data Format Manual • Installation Requirements • Installation • Diagnostics and Maintenance • Error Analysis • Principle of Operation • SCSI Bus SCSI Physical • SCSI Message Interface • Error Recovery Specifications •...
CONTENTS page CHAPTER 1 SCSI BUS .........................13 System Configuration ........................13 Interface Signal Definition ........................15 Physical Requirements ........................19 1.3.1 Interface connector ..........................20 1.3.2 Interface cable ..........................27 Electrical Requirements........................29 1.4.1 Single-Ended type ...........................29 1.4.2 Low-Voltage Differential type ......................32 1.4.3 Internal terminal resistor and power supply for terminating resistor ..........35 1.4.4 Usage in 8-bit/16-bit transfer mode....................37 1.4.5...
Bus Conditions ..........................105 1.7.1 ATTENTION condition ........................105 1.7.2 RESET condition...........................108 Bus Phase Sequence ........................109 1.8.1 Bus Phase Sequence with Information Units Disabled ..............109 1.8.2 Phase sequences with information unit enabled ................117 126.96.36.199 Phase sequences for physical reconnection or selection without using attention condition..117 188.8.131.52 Phase sequences for selection using attention condition ...............118 SPI information units........................119 1.9.1...
FIGURES page Figure 1.1 Example of SCSI configuration ....................14 Figure 1.2 Interface signals ........................15 Figure 1.3 DATA BUS and SCSI ID .......................16 Figure 1.4 SCSI interface connector (HDD side) (16-bit SCSI) ..............20 Figure 1.5 SCSI interface connector (cable side) (16-bit SCSI) ..............21 Figure 1.6 Single-ended connector pin assignment (16-bit SCSI) ............22 Figure 1.7...
Figure 1.34 DT DATA IN phase training pattern ..................90 Figure 1.35 DT DATA OUT phase training pattern ..................92 Figure 1.36 Usage of P1 to establish data valid and data invalid states .............93 Figure 1.37 READ STREAM and WRITE FLOW..................96 Figure 1.38 Data sequence at data transfer....................99 Figure 1.39 Data transfer rate in synchronous mode................101 Figure 1.40 Switching direction of transfer over data bus ...............103 Figure 1.41 ATTENTION condition......................107...
TABLES page Table 1.1 INFORMATION TRANSFER phase identification...............18 Table 1.2 Single-Ended maximum distance between terminators ............19 Table 1.3 LVD maximum distance between terminators................20 Table 1.4 SE and LVD Transmission line impedance of cable at maximum indicated data transfer rate ..........................27 Table 1.5 Attenuation Requiaments for SCSI cable media..............27 Table 1.6...
Table 1.33 Maximum capacitance ......................150 Table 1.34 System level requirements ....................151 Table 2.1 SCSI message........................155 Table 2.2 Extended message.........................156 Table 2.3 Definition of data transfer mode by message exchange............169 Table 2.4 Synchronous mode data transfer request setting..............171 Table 2.5 Transfer mode setup request from INIT to HDD..............173 Table 2.6 Transfer mode setup request from HDD to INIT..............175 Table 2.7...
CHAPTER 1 SCSI BUS System Configuration Interface Signal Definition Physical Requirements Electrical Requirements Timing Rule Bus Phases Bus Conditions Bus Phase Sequence SPI information units 1.10 SCAM 1.11 Ultra SCSI 1.12 Low-Voltage Differential 1.13 SCSI Bus Fairness This chapter describes the configuration, physical and electrical characteristics, interface protocol, and operations of SCSI buses.
Any SCSI ID of the HDD can be selected using the setup pins. However, the LUN is fixed to zero (0). The SCSI ID can be 0 to 15. Note: The maximum number of SCSI devices and the maximum cable length are limited depending on the selected SCSI data transfer mode and the SCSI transceiver type.
Interface Signal Definition Figure 1.2 shows interface signal types. The SCSI bus consists of 27 signal lines. The 27 signal lines consist of data buses (2 bytes plus two odd parity bits) and 9 control signal lines. The SCSI bus can be a single-ended or low voltage differential(LVD) interface depending on the model used.
DB15 to DB00, P1, P_CRCA (Data buses) The 16-bit SCSI system uses a bidirectional data bus consisting of two-byte data and two odd parity bits. MSB (2 ): DB15, LSB (2 ): DB00 The data bus is used to transfer a command, data, a status, or a message in the INFORMATION TRANSFER phase.
(d) P1 (data group transfer enabled) A signal that shall be continuously negated by the SCSI device driving the DB(15-0) signals and shall be ignored by the SCSI device receiving the DB(15-0) signals during DT DATA phases. (e) P1 (information unit and paced transfer enabled) A signal that is sourced by SCSI device to indicate the data valid or data invalid state.
BSY (BUSY) The BSY signal indicates that the SCSI bus is in use. In the ARBITRATION phase, this signal is used to request for the bus usage priority. SEL (SELECT) The SEL signal is used by the INIT to select a TARG (in the SELECTION phase) or by the TARG to reselect an INIT (in the RESELECTION phase).
REQ (REQUEST) This is a transmission request from the TARG to the INIT in the INFORMATION TRANSFER phase. ACK (ACKNOWLEDGE) The ACK signal is a response to the REQ signal sent from the INIT to TARG in the INFORMATION TRANSFER phase. ATN (ATTENTION) The ATN signal indicates that the INIT has a message to be sent to the TARG.
Table 1.3 LVD maximum distance between terminators Maximum distance between terminators (meters) Interconnect Fast-5 Fast-10 Fast-20 Fast-40 Fast-80 Fast-160 Point-to-point Multidrop 1.3.1 Interface connector Interface connector of the 16-bit SCSI The HDD 16-bit SCSI bus connector is nonshielded 68-pin, consisting of two 34-pin rows with adjacent pins 1.27 mm (0.05 inch) part (Figure 1.4).
Interface connector of SCA-2 type 16-bit SCSI The 16-bit, SCA-2 type SCSI bus connectors of the HDD are 80-pin, unshielded connectors, each having two rows of 40 parallel pins (separated 1.27 mm or 0.05" from each other) (see Figure 1.8). Figure 1.9 shows the pin assignment of 16-bit, SCA-2 type single-ended SCSI interface connector.
1.3.2 Interface cable Use the twisted-pair interface cables satisfying the requirements of Tables 1.4 and 1.5. Table 1.4 SE and LVD Transmission line impedance of cable at maximum indicated data transfer rate Local SE transmission line Local differential Description impedance transmission line impedance Minimum Maximum...
Electrical Requirements 1.4.1 Single-Ended type Termination circuit All signals except for RESERVE, GND, or TERMPWR should be terminated at both ends of the bus. Each signal should be terminated by one of the following methods. Figures 1.12 and 1.13 show the termination circuit. a) Each signal must connect to the TERMPWR signal through 220 Ω...
The HDD uses the terminator circuit satisfying conditions (b) above. The INIT terminator circuit is also recommended to meet conditions (b) above. (P_CRCA) Figure 1.13 Single-Ended SCSI termination circuit-2 C141-C015...
Driver and receiver For the interface signal driver, an open-collector or tri-state buffer that satisfies the following output characteristics is used. All signals are negative logic (true = "L"). The receiver and non-driver of the SCSI device under the power-on state should satisfy the following input characteristics on each signal.
The SCSI device under the power-off state should satisfy the characteristics of I and I [Recommended circuit example] Driver: MB463 (Fujitsu) or SN7438 (TI) (Open-collector NAND gate) Receiver: SN74LS240 or SN74LS19 (TI) (Shumitt trigger input inverter) 1.4.2 Low-Voltage Differential type Termination circuit All signals except for GROUND and TERMPWR should be terminated at both ends of the bus.
DIFFSENS a) DIFFSENS driver The LVD DIFFSENS driver sets a voltage level on the DIFFSENS line that uniquely defines a LVD transmission mode. LVD terminators and multimode terminators shall provide a LVD DIFFSENS driver according to the specifications in Table 1.8. Table 1.8 LVD DIFFSENS driver specifications Value...
a) The device is capable of logical operation for at least 100 ms, and Notes: The 100 ms delay allows time for the DIFFSENS pin to connect after the initial power connection (in the case of insertion of a device into an active system), or allows time for the power distribution system to settle.
MATED 1/Backplane Side The signal shall be held to a ground level when the MATED 2 connection is completed. The MATED 1 signal shall be held to the open level when the MATED 2 connection is not completed. MATED 2 connection Figure 1.15 Circuit for mated indications 1.4.3...
Figure 1.16 shows the configuration of a SCSI terminating resistor circuit. The circuit shall be set in either mode (by the CN2 setup pin) depending on the HDD system requirements. 16-bit SCSI (P-connector) setting terminal CN2 23-24pin Supply TERMPWR to SCSI Bus Short Don't supply TERMPWR to SCSI Bus Open...
1.4.4 Usage in 8-bit/16-bit transfer mode When the HDD is used as 8-bit SCSI device, it is connected terminating resistor circuit to upper 8- bit and parity (DB08 to DB15 and DBP1) or short set up pin (CN2 13-14). When the HDD is used as 16-bit SCSI device, leave the set up pin Jumper setting "8/16"...
1.4.5 Signal driving conditions Signal status value Table 1.12 shows the correspondence between the input interface signal level at the receiving end and its logic state. Table 1.12 Signal status at receiving end Single-ended type signal state LVD type signal Logic state Asynchronous, state...
Signal sources Table 1.14 lists SCSI device types (or signal sources) which can drive signals in each interface operating phase. Table 1.14 Bus phases and signal sources I/O, REQ, DB15-8, DB7-0 P_CRCA C/D, DBP1 BUS FREE ARBITRATION QAS ARBITRATION SELECTION I&T RESELECTION I&T...
Timing Rule 1.5.1 Timing value Table 1.15, 16, 17 give the timing required for operations on the SCSI bus. Table 1.15 SCSI bus control timing values Timing description Type Timing values 2.4 μs Arbitration delay Bus clear delay 800 ns Bus free delay 800 ns 1.6 μs...
Table 1.16 SCSI bus data & information phase ST timing values Timing values [ns] (5) Timing description Type Async Fast-5 Fast-10 Fast-20 Fast-40 ATN Transmit Setup Time min. 21.5 19.25 ATN Receive Setup Time min. 6.75 Cable Skew (3) max. Receive Assertion Period (4) min.
Table 1.18 SCSI bus data & information phase DT timing values Timing values [ns] (12) Timing description Type Fast-10 Fast-20 Fast-40 Fast-80 Fast-160 ATN transmit setup time 48.4 29.2 19.6 14.8 Flow control transmit hold time 38.4 19.2 Flow control transmit setup time 48.4 29.2 19.6...
Table 1.19 Receive SCSI bus data & information phase DT timing values Timing values [ns] (15) Timing description Type Fast-10 Fast-20 Fast-40 Fast-80 Fast-160 ATN receive setup time 13.6 3.45 Flow control receive hold time 11.6 1.45 Flow control receive setup time 18.6 12.8 8.45...
ATN transmit setup time The minimum time provided by the transmitter between the assertion of the ATN signal and the negation of the ACK signal. Specified to provide the increased ATN receive setup time, subject to intersymbol interference, cable skew, and other distortions. ATN receive setup time The minimum time required at the receiver between the assertion of the ATN signal and the negation of the ACK signal to recognize the assertion of an Attention Condition.
Cable skew The maximum difference in propagation time allowed between any two SCSI bus signals measured between any two SCSI devices excluding any signal distortion skew delays. Data release delay The maximum time for an initiator to release the DATA BUS, DB(P_CRCA), DB(P1) signals following the transition of the I/O signal from false to true.
(18) System deskew delay The minimum time that a SCSI device should wait after receiving a SCSI signal to ensure that any signals transmitted at the same time are valid. The system deskew delay shall not be applied to the synchronous data transfers.
(24) Signal timing skew The maximum signal timing skew occurs when transferring random data and in combination with interruptions of the REQ or ACK signal transitions (e.g., pauses caused by offsets). The signal timing skew includes cable skew (measured with 0101...patterns) and signal distortion skew caused by random data patterns and transmission line reflections.
(30) Transmit REQ (ACK) period tolerance The maximum tolerance that a SCSI device may subtract from the negotiated synchronous period. The tolerance comprises the transmit REQ (ACK) tolerance plus a measurement error due to noise. (31) pCRC Receive hold time The minimum time required at the receiver between the transition of the REQ signal and the transition of the P_CRCA signal while pCRC protection is enabled.
(37) Transmit REQ assertion period with P_CRCA transitioning The minimum time that a target shall assert the REQ signal during a DT DATA phase while transitioning P_CRCA with pCRC protection enabled. Specified to provide the increased receive REQ assertion period, subject to loss on the interconnect.
(44) De-skewed data valid window The minimum difference in time allowed between the rising or falling edge of a "1010..." pattern on the DATA BUS or DB(P1) and its clocking signal on the ACK or REQ signal as measured at their zero-crossing points after skew compensation is applied by the receiver without allowing any error in the received data (see Fig.1-17).
(48) Flow control receive setup time The maximum time required by the SCSI INIT port between the assertion of the P_CRCA signal and the assertion of the REQ signal corresponding to the last iuCRC transfer of a SPI data stream information unit.
(54) Transmit ISI Compensation The effective reduction in worse case ISI timing shift provided by the transmitting SCSI device as seen at the receiving SCSI device connector. (55) Transmitter skew The maximum difference in time allowed between the rising or falling edge of a "1010..." pattern on the DATA BUS or DB(P1) signal and its clocking signal on the ACK or REQ signal as measured at their zero-crossing points (see Fig.1-18).
(56) Transmitter time asymmetry The maximum time on DATA BUS, DB(P1), ACK, or REQ signal from any transition edge to the subsequent transition edge during a "1010..." pattern, as measured at their zero-crossing points, minus the data transfer period (see Fig.1-19). Figure 1.19 Transmitter time asymmetry C141-C015...
1.5.2 Measurement point (1) SE Fast-5/10 The measurement point of Fast-5/10 is different from that of Fast-20. The Figure 1.20 is the Fast- 5/10 measurement point. Figure 1.20 Fast-5/10 Measurement Point C141-C015...
(3) LVD ST Data Transfer Figure 1.22 is the LVD ST Data Transfer measurement point. ** Use the crossing that yield the shorter Assertion Period and Negation Period. Figure 1.22 LVD ST Data Transfer measurement point Notes: 1. V - negated signal 2.
(4) LVD DT Data Transfer Figure 1.23 is the LVD DT Data Transfer measurement point. Figure 1.23 LVD DT Data Transfer measurement point Notes: 1. V - negated signal 2. V - asserted signal 3. t = 1.25ns minimum 4. V or V are required to drive the 100 mV at the leading edge of the transition.
Bus Phases The SCSI bus must be in one of the following eight phases: • BUS FREE phase • ARBITRATION phase • SELECTION phase • RESELECTION phase • COMMAND phase • DATA phase INFORMATION TRANSFER phase • STATUS phase • MESSAGE phase The SCSI bus can never be in more than one phase at any given time.
1.6.1 BUS FREE phase All SCSI devices do not use the bus in the BUS FREE phase. SCSI devices shall detect the BUS FREE phase after SEL and BSY signals are both false for one Bus Settle Delay. SCSI devices which have detected the BUS FREE phase shall release all bus signals within one Bus Clear Delay after BSY and SEL signals become false for Bus Settle Delay.
The SCSI bus enters the BUS FREE phase when the TARG stops the BSY signal in one of the following events: • When RESET condition has been detected. • When TARG has received the following message normally. ABORT TASK, ABORT TASK SET, CLEAR TASK SET, LOGICAL UNIT RESET, TARG RESET, CLEAR ACA •...
3) Then the SCSI device that arbitrates the bus asserts the DATA BUS bit corresponding to its own SCSI ID and BSY signal (*1) within Bus Set Delay after the last observation of the BUS FREE phase. 4) After waiting at least Arbitration Delay since the SCSI device asserted BSY signal, the SCSI device shall examine the value on the DATA BUS to determine the priority of the bus arbitration (*1).
184.108.40.206 QAS ARBITRATION QAS protocol QAS allows a TARG with an information unit transfer agreement in effect and QAS enabled (see 2.3.22 that is currently connected to an INIT that has QAS enabled to transfer control of the bus to another SCSI device that has QAS enabled without an intervening BUS FREE phase.
4) If the INIT creates an attention condition then the TARG will go to a MESSAGE OUT phase, receive all the message bytes, and cause an unexpected bus free by generating a BUS FREE phase. 5) If the TARG detects the SEL signal being true, the TARG will release the BSY, MSG, C/D, and I/O signals within one QAS release delay.
The SCSI ID bit is a single bit on the DATA BUS that corresponds to the SCSI device's unique SCSI address. All other DATA BUS bits shall be released by the SCSI device. The DB(P_CRCA) and DB(P1) are not valid during the QAS phase. During the QAS phase, DB(P_CRCA), and DB(P1) may be released or asserted, but shall not be actively driven false.
Note: If single INIT operates without the RESELECTION phase, it is allowed to assert only the TARG's SCSI ID. 3) After waiting at least Deskew Delay × 2, the INIT asserts SEL signal and waits the response (BSY signal) from the TARG. Start sequence with ARBITRATION phase In systems with ARBITRATION phase implemented, the INIT starts the SELECTION phase in the following sequence (see Figure 1.28).
The TARG must response to the INIT by asserting the BSY signal within Selection Abort Time since the TARG detects that the TARG is selected. If the SCSI ID with three or more bits is detected, or if a parity error is detected under the system that the parity bit is enabled, the TARG shall not respond to the SELECTION phase.
1.6.4 RESELECTION phase The SCSI device operated as a TARG selects an INIT in the RESELECTION phase. This phase is an option for the system, and this phase can only be used in systems with the ARBITRATION phase implemented. When the TARG re-starts the command processing under the disconnection on the SCSI bus, the TARG reconnects with the INIT using this phase.
Response sequence If a SCSI unit (INIT to be selected) detects the SEL and I/O signals and data bus bit (DBn) corresponding to the own SCSI ID are all true and if it detects the BSY signal which is false for at least Bus Settle Delay, the SCSI unit shall recognize that it is selected in the RESELECTION phase.
Timeout procedure If the TARG cannot detect a response (BSY signal) from the INIT when the Selection Timeout Delay or longer has passed after starting the RESELECTION phase, the timeout procedure shall be performed though one of the following schemes: 1) The TARG asserts the TRUE signal and generates an RESET condition.
1.6.5 INFORMATION TRANSFER phases The COMMAND, DATA, STATUS and MESSAGE phases are generally called the INFORMATION TRANSFER phase. This phase can transfer the control information and data between the INIT and TARG via the data bus. The type of INFORMATION TRANSFER phase is determined by the combination of C/D, I/O, and MSG signals (see Table 1.1).
Notes: After the ACK signal becomes false in the current INFORMATION TRANSFER phase, the TARG can start preparing a new phase by changing the status of C/D, I/O and MSG signals. The status of these three signals can change in any order or at once. The status of one signal may change more than once;...
b. Transfer from INIT to TARG When the I/O signal is false, the information of the data bus is transferred from the INIT to the TARG. The following explains the information transfer sequence. The TARG asserts the REQ signal to request the INIT for information transfer. The INIT asserts the ACK signal at least one System Deskew Delay + Cable Skew Delay after sending valid information of the requested type on the data bus.
c. Improved Error Detection for the Asynchronous Information Phases (AIP) The COMMAND, MESSAGE and STATUS asynchronous information transfer phases except DATA phase only transfer information on the lower eight data bits of a SCSI bus with only normal parity protection on those transfers. In this improved detection additional check information can be transferred on the upper eight data bits.
Note: The HDD supports up to 20 MHz (40 MHz on LVD) of synchronous data transfer (see Table 1.7). The default data transfer mode is asynchronous. When the power is first turned on, the system is reset, or after the TARGET RESET message has been issued, data is transferred in the asynchronous mode only.
1) The INIT detects a REQ assertion. 2) The INIT first drives the DB(7-0,P_CRCA) or DB(15-0,P_CRCA,P1) signals to their values. 3) The INIT delays at least one Transmit Setup Time. 4) The INIT asserts the ACK signal. 5) The INIT holds the DB(7-0,P_CRCA) or DB(15-0,P_CRCA,P1) signals valid for at least one Transmit Hold Time after the assertion of the ACK signal.
[Timing rule for TARG to INIT] Min. Transmit Assertion Period Min. Receive Hold Time Min. Transmit Min. Transmit Setup Time Hold Time [Timing rule for INIT to TARG] Min. Transmit Assertion Period Min. Receive Hold Time Min. Transmit Min. Transmit Setup Time Hold Time Figure 1.32 ST transfer in synchronous mode...
DT synchronous data transfer When a DT data transfer agreement has been established the target shall only use the DT DATA IN phase and DT DATA OUT phase for data transfers. The DT synchronous data transfer is available only when it has been defined between the INIT and TARG by exchanging the PARALLEL PROTOCOL REQUEST message with each other.
5) INIT fetches the values from DB(15-0) signals within a receive hold time of the transition of the REQ signal and it also fetches the value from the P_CRCA signal within a pCRC receive hold time of the transition of the REQ signal. Then INIT responds with an ACK transition.
9) TARG drives the DB(15-0) signals to their desired pCRC values and waits at least one transmit setup time. 10) TARG negates the REQ signal and holds the DB(15-0) signals for a minimum of one transmit hold time and the P_CRCA signal asserted for at least a pCRC transmit hold time. 11) TARG holds the REQ signal negated for at least one transmit REQ negation period with P_CRCA transitioning since the last REQ negation.
If received pCRC and computed pCRC do not match (i.e., a pCRC error is detected), or if an improperly formatted data group is transferred, then the INIT creates an attention condition or before the last transfer of the pCRC field. When the TARG switches to a MESSAGE OUT phase the INIT sends an INITIATOR DETECTED ERROR message to the TARG.
When the INIT detects an assertion of the P_CRCA signal and the REQ signal is negated (i.e., no pad field required), INIT transfers data bytes for all outstanding REQs received prior to the REQ that had the P_CRCA signal asserted. INIT drives the DB(15-0) signals to their desired pCRC values. INIT delays at least one transmit setup time, asserts the ACK signal and holds the DB(15- 0) signals valid for a minimum of one transmit hold time and the ACK signal asserted for a minimum of a transmit assertion period.
<Pad field required> transmit setup transmit hold transmit REQ assertion transmit REQ negation period with pCRCA period with pCRCA transmit negation transmit assertion transitioning transitioning period period + 100 mV - 100 mV DB15-0 data value pad value pCRC value pCRC value + 100 mV P_CRCA...
220.127.116.11 Paced transfer Paced transfer overview If a paced transfer agreement has been established it shall be used in DT DATA phase and information unit transfers shall be used. The transfer agreement also specifies the REQ/ACK offset and the transfer period. When paced transfers are being used data shall be transferred using DT data transfers on 16-bit wide buses that transmit and receive data using LVD transceivers.
If the retain training information is enabled and a port changes from a INIT to a TARG that TARG shall retrain if the saved training configuration values were saved while the port was a INIT. The receiving SCSI device shall use some or all elements of the training pattern to achieve deskewing.
keep the P1, P_CRCA, and DB(15-0) signals negated while continuing to assert and negate REQ at the negotiated transfer period for the equivalent of 8 transfer periods (e.g., 50 ns at fast-160); keep the P1, P_CRCA, DB(15-0), and REQ signals negated for the equivalent of 8 additional transfer periods;...
Figure 1.34 DT DATA IN phase training pattern (b) DT DATA OUT phase training pattern The TARG requests a training pattern on a DT DATA OUT phase by asserting the SEL signal a minimum of two system deskew delays before asserting the REQ signal. The TARG begins its training sequence by transmitting the following training pattern: if precompensation is enabled then set the drivers to the strong driver state;...
The INIT shall begin the section A of its training pattern independent of the start of the TARGs training pattern if it detects the SEL and MSG true, and C/D and I/O false on the first assertion of the REQ signal. The INIT shall transmit the following training pattern: Start of section A: if precompensation is enabled then set the drivers to the strong driver state;...
Figure 1.35 DT DATA OUT phase training pattern P1 data valid/invalid state transitions The transmitting SCSI device port shall indicate the start of a data valid state by reversing the phase of the P1 signal coincident with a REQ or ACK assertion. This is accomplished by withholding the next transition of P1 at the start of the first two transfer periods of valid data.
Figure 1.36 Usage of P1 to establish data valid and data invalid states (a) Starting pacing transfers at end of training pattern See (2) Paced transfer training pattern for the description of starting a data valid state after a training pattern. (b) Starting pacing transfers with no training pattern Before starting the DT DATA IN phase the TARG will wait at least two system deskew delays after the SEL signal is negated before the first assertion of the REQ signal.
the TARG may establish a data valid state by changing the phase of P1. The DT DATA OUT phase without training starts on the first assertion of REQ if the SEL is not asserted. The TARG begins pacing transfers only after meeting all the following: signal restrictions between information transfer phases;...
drives the DB(15-0) signals to their values simultaneous with the next REQ signal negation; and holds the DB(15-0) signals valid for a minimum of one transmit hold time. If the I/O signal is true (i.e., transfer to the INIT), to receive SPI information units the INIT shall: Read the value on the DB(15-0) signals within one receive hold time of the transition of the REQ signal;...
Read Stream The assertion of the REQ signal corresponding to the last iuCRC transfer last packet of data stream DB15-0 iuCRC iuCRC (if Pad is not required) Flow control Flow control setup time hold time P_CRCA <Earliest assertion of P_CRCA> <Slowest negation of P_CRCA>...
(6) DT DATA phase information unit transfer exception condition handling When information unit transfers are enabled (see Section 1.9): (a) DT DATA IN phase The INIT shall not negate the ACK for the last byte of the last iuCRC in an information unit until the entire information unit has been verified and any required attention condition has been established.
The TARG shall only respond to an iuCRC error after all the data in an information unit has been received. If the nexus has been fully identified (i.e., an I_T_L_Q nexus has been established) and the TARG detects an iuCRC error in any SPI data information unit, SPI data stream information unit, or last command SPI command information unit it receives while in the DT DATA OUT phase the TARG shall switch to a DT DATA IN phase and send a SPI L_Q/SPI status information unit pair to the INIT, before sending any other SPI L_Q information unit.
Number of information P cable items transferred Unused "8-bit mode" Unused DB15....DB8 DB7....DB0 "16-bit mode" Figure 1.38 Data sequence at data transfer 1.6.6 COMMAND phase The COMMAND phase is a bus phase in which the TARG requests the INIT to transfer command information (CDB) to the TARG.
Data transfer rate in synchronous mode Table 1.20 lists the synchronous transfer mode parameters valid for the HDD. The actual values are determined by exchange of SYNCHRONOUS DATA TRANSFER REQUEST or PARALLEL PROTOCOL REQUEST message between the two SCSI devices. If two or more INITs are used, different parameters may be used by each INIT.
(4) Ultra-160M fast synchronous data transfer mode only for LVD (Fast-80 SCSI). This code is only valid if the PROTOCOL OPTIONS field has a value selected that supports double- transition data transfers. (5) Ultra-320 fast synchronous data transfer mode only for LVD (Fast-80 SCSI). This code is only valid if the PROTOCOL OPTIONS field has a value selected that supports double-transition and information units transfer.
MESSAGE OUT phase In a MESSAGE OUT phase, the TARG requests to transfer message information from the INIT to the TARG. The TARG keeps the C/D and MSG signals true and I/O signal false during REQ/ACK handshaking in this phase. The TARG executes this phase in response to the ATTENTION condition (described in Section 1.7.1) created by the INIT, and must remain in the MESSAGE OUT phase.
1) The TARG negates the I/O signal. 2) The TARG releases the DB(15-0, P_CRCA and/or P1) within one System Deskew Delay. 3) The INIT detects the negation of the I/O signal. 4) The INIT asserts the DB(15-0, P_CRCA and/or P1) more than one System Deskew Delay. f) The P_CRCA signal direction may switch direction while the DATA BUS and/or DB(P1) does not (e.g., changing from COMMAND phase to DT DATA OUT phase).
The HDD has a time monitoring feature for the SCSI bus to prevent the hang-up of the SCSI bus in the case that the HDD cannot receive a response from the INIT in the RESELECTION phase. The HDD monitors the response from the INIT (BSY signal) in the RESELECTION phase. When the HDD cannot receive the response within a specified period (250 ms), the HDD executes the timeout process (see Section 1.6.4) and releases the SCSI bus once.
Bus Conditions Two types of asynchronous control, the ATTENTION condition and RESET condition, shall be defined to control or modify the bus phase transition sequence (bus conditions). 1.7.1 ATTENTION condition The ATTENTION condition allows the INIT to report that the INIT has a message to be sent to the TARG.
When the ATN signal becomes true in the COMMAND phase, the TARG shall start the MESSAGE OUT phase immediately after a part or all bytes of command (CDB) has been transferred. When the ATN signal becomes true in the DATA phase, the TARG shall start the MESSAGE OUT phase immediately after the DATA phase.
Min. System ATN transmit setup time. Deskew Delay × 2 Figure 1.41 ATTENTION condition Note: The ATTENTION condition generated by the INIT determines the message level to be used in the command execution sequence. (Details are explained in Section 2.1.3.) If the ATTENTION condition is not generated, the TARG uses a TASK COMPLETE message only.
1.7.2 RESET condition The RESET condition allows all SCSI devices to release immediately from the bus. RESET has higher priority than any other phases and bus conditions. Any SCSI device can generate the RESET condition anytime by keeping the RST signal true for Reset Hold Time or more. The state of all bus signals except RST signals are undefined during the RESET condition.
Figure 1.42 RESET condition Bus Phase Sequence 1.8.1 Bus Phase Sequence with Information Units Disabled The SCSI bus phases are switched in the specific sequence depending on the command execution by the TARG. When the TARG asserts the BSY signal true in the SELECTION or RESELECTION phase, the status change of SCSI bus is controlled by the TARG except for the ATTENTION and RESET conditions.
1.8.2 Phase sequences with information unit enabled 18.104.22.168 Phase sequences for physical reconnection or selection without using attention condition The sequences for physical reconnection or selection without using attention condition while an information unit transfer agreement is in effect shall be as shown in Figure 1.45. The normal progression for selection without using attention condition (see 10.5.3) if QAS is disabled is: from BUS FREE to ARBITRATION:...
22.214.171.124 Phase sequences for selection using attention condition The sequences for a selection with attention condition while an information unit transfer agreement is in effect shall be as shown in Figure 1.46. The normal progression for selection using attention condition (see 10.5.2.3) if QAS is disabled is: from BUS FREE to ARBITRATION;...
SPI information units 1.9.1 SPI information unit overview An information unit transfer transfers data in SPI information units. The order in which SPI information units are transferred within an information unit transfer follows a prescribed sequence. When information unit transfers are enabled only SPI information units shall be transferred within the DT DATA OUT phase and DT DATA IN phase.
the last SPI data stream information unit. At completion of those SPI information units the I_T_L_Q nexus becomes an I_T nexus. The I_T nexus remains in place until the TARG does a physical disconnect or an I_T_L_Q nexus is reestablished by the TARG transmitting a SPI L_Q information unit. Logical reconnections occur on the successful TARG transmission and INIT receipt of a SPI L_Q information unit for an existing I/O process.
1.9.3 SPI information units 126.96.36.199 SPI command information unit The SPI command information unit (see table 1.22) transfers CDBs, task attributes, and task management requests to be performed by a device server. An INIT shall consider a BUS FREE phase after the transfer of a SPI command information unit to be equivalent to receiving a DISCONNECT message.
Table 1.22 SPI command information unit Byte Reserved Reserved TASK ATTRIBUTE TASK MANAGEMENT FUNCTIONS ADDITIONAL CDB LENGTH = (number of additional CDB bytes)/4 RDDATA WRDATA ADDITIONAL CDB (MSB) IUCRC (LSB) The TASK ATTRIBUTE field is defined in table 1.23. Table 1.23 TASK ATTRIBUTE Codes Description...
Table 1.24 TASK MANAGEMENT FUNCTIONS Codes Description Indicates no task management requests for the current task. The task manager shall abort the task as defined in the ABORT TASK Message. The task manager shall abort the task set as defined in the ABORT TASK SET message.
188.8.131.52 SPI L_Q information unit The SPI L_Q information unit (see table 1.25) contains L_Q nexus information for the information unit that follows, the type of information unit that follows, and the length of information unit that follows. A SPI L_Q information unit shall precede all SPI command information units, SPI multiple command information units, SPI data information units, SPI status information units, and the first of an uninterrupted sequence of SPI data stream information units.
Table 1.26 TYPE Codes Type Description Last Sent by a SCSI initiator device to indicate a SPI command information unit Command shall follow this SPI L_Q information unit. Indicates the SCSI initiator device shall not send any more SPI command information units during the current connection.
The LOGICAL UNIT NUMBER field specifies the address of the logical unit of the I_T_L_Q nexus for the current task. The structure of the logical unit number field shall be as defined in the SCSI Architecture Model-2 standard. If the addressed logical unit does not exist, the task manager shall follow the SCSI rules for selection of invalid logical units as defined in the SCSI Primary Commands-3 standard.
184.108.40.206 SPI data information unit The SPI data information unit (see table 1.28) contains data. The detection of a BUS FREE phase following a SPI data information unit by an INIT shall be equivalent to the INIT receiving a DISCONNECT message. The detection of a QAS REQUEST message following a SPI data information unit by a INIT shall be equivalent to the INIT receiving a DISCONNECT message.
may change the C/D, I/O, or MSG signals on a SPI data stream information unit boundary. If during the last SPI data stream information unit, of a read stream, the P_CRCA signal was not asserted and an INIT detects a REQ transition after receiving the last iuCRC for a SPI data stream information unit that INIT shall receive the next SPI data stream information unit.
220.127.116.11 SPI status information unit The SPI status information unit (see table 1.30) contains the completion status of the task indicated by the preceding SPI L_Q information unit. The TARG considers the SPI status information unit transmission to be successful when there is no attention condition on the transfer of the information unit.
If sense data is provided, SNSVALID will be set to one and the SENSE DATA LIST LENGTH field will specify the number of bytes in the SENSE DATA field. The SENSE DATA LIST LENGTH field only contains even lengths greater than zero and not be set to a value greater than 252.
Table 1.32 PACKETIZED FAILURE CODE Codes Description NO FAILURE Reserved SPI COMMAND INFORMATION UNIT FIELDS INVALID Reserved TASK MANAGEMENT FUNCTION NOT SUPPORTED TASK MANAGEMENT FUNCTION FAILED INVALID TYPE CODE RECEIVED IN SPI L_Q INFORMATION UNIT ILLEGAL REQUEST RECEIVED IN SPI L_Q INFORMATION UNIT Reserved.
1.10 SCAM The HDD does not support the SCAM functions. 1.10.1 SCAM operations The SCAM operation functions include all functions required for ID assignment of each SCAM device so that the SCAM tolerant and SCAM devices are identified by the SCAM initiator and target.
The dominant SCAM initiator can classify and assign SCSI IDs in various ways as described below. • SCSI ID classification After the reset, the dominant SCAM initiator waits for a certain period to establish a delay time between the reset and selection of SCAM tolerant. The dominant SCAM initiator initializes the SCSI ID internal table and indicates that all SCSI IDs are not classified yet.
Level-1 SCAM target Figure 1.51 shows the operations of level-1 SCAM target. Its status names are explained later. The RESET condition can terminate all operations in any status, and it forces the SCAM target to the Reset Delay status. Power-on Reset Power-on Delay Reset Delay...
Note: The SCAM target may not recognize the Configuration Process Complete function code at the end of SCAM protocol, and may return to the SCAM Monitor status. The SCAM target in the ID Unassigned status is the one to which no SCSI ID has been assigned both explicitly and implicitly.
The SCAM target enters the Power-On Delay status immediately after the power-on, and allows the local initialization to start. The SCAM target shall exit this status, and enter the Initial SCAM Protocol status within a SCAM power-on to SCAM selection delay. During Initial SCAM Protocol status, the level-2 SCAM target arbitrates the SCSI bus without using the ID and performs the SCAM selection.
When two buses having the different width are interconnected, the DATA BUS signal of the bus having a larger width shall be terminated with an adapter. The connector has been designed to electrically isolate the A and P shielded connectors from each other. Two reserved lines (having A-cable contact numbers 23 and 24) and the open lines (having A- cable contact number 25) on the A cable are the TERMPWR lines (having the P-cable contact numbers 33, 34 and 35) on the P cable.
The ground offset voltage between logical ground terminals on any two device connectors shall be less than 50 mV. 1.11.3 Electrical characteristics of SCSI parallel interface The Fast-20 parallel interface shall have one of the following electrical characteristics: 1) Either conductor of single-ended driver and receiver, and each signal pair shall be active, and the other conductor shall be grounded.
Note: These requirements shall be satisfied if any device supplies the TERMPWR. b. Single-ended output signal characteristics An active negate driver shall be used for single-ended line signals. This driver can be in the Assert, Negate, or High-Impedance state. Each signal supplied by the SCSI device shall have the following output characteristics when measured at the connector position of SCSI device: (Low-level output voltage) = 0.0 to 0.5 VDC if I =48 mA (Signal assert state)
[mA] 3.24 Notes: This Figure shows the operation areas allowed for DC output characteristics of active negate driver if negated. This Figure does not show the AC output characteristics. The AC output characteristics may vary depending on the other requirements including the slew rate specifications.
SCSI driver 47Ω±5% 2.5 V – Figure 1.54 Single-ended test circuit c. Single-ended signal input characteristics All SCSI units (including both the receivers and disable drivers) shall meet the following electrical signal characteristics during power-on: (Low-level input voltage) = 1.0 VDC Max (True signal) (High-level input voltage) = 1.9 VDC Min (False signal) (Low-level input current) = +/-20 μA if V =0.5 VDC...
Low-Voltage Differential 1.12.1 Ultra2-SCSI The SPI-2, Fast-40 Standard defines the characteristics of cables, signals, and transceivers required for 40 MB/s signal transmission. The services required to communicate with a higher layer protocol is defined by the SPI-2. In addition, the expansion to SPI-2 parallel interface is defined to enhance the available data transfer rate.
The Pased transfer mode in detail is written in Subsection 18.104.22.168. The Information unit trasfer in detail is written in Subsection 1.9. 1.12.4 LVD driver characteristics The LVD driver shall provide balanced asymmetrical sources that provide current from positive supply voltage to one signal line while sinking the same current to ground from the other signal line as shown in Figure 1.55 Diagonally opposite sources operate together to produce a signal assertion or a signal negation.
1.12.6 LVD capacitive loads There are three components to differential SCSI bus capacitive loading: –Signal to local ground (C1), +Signal to local ground (C2), and –signal to +signal (C3) as shown in Figure 1.57. The values C1, C2, and C3 represent measurements between the indicated points and do not represent discrete capacitors.
Table 1.33 Maximum capacitance Capacitance measurement Max. Notes @V=0.7 to 1.8 VDC -Signal/GND C1(pF) REQ, ACK and DB(15-0,P_CRCA,P1) @V=0.7 to 1.8 VDC -Signal/GND C2(pF) REQ, ACK and DB(15-0,P_CRCA,P1) @V=0.7 to 1.8 VDC -Signal/GND C3(pF) REQ, ACK and DB(15-0,P_CRCA,P1) @V=0.7 to 1.8 VDC -Signal/GND C1(pF) all other signals @V=0.7 to 1.8 VDC -Signal/GND...
Table 1.34 System level requirements Parameter Minimum Maximum (except OR-tied signals) (1) -1 V -100 mV (except OR-tied signals) (1) 100 mV (OR-tied signals) (1) -3.6 V -100 mV (OR-tied signals) (1) 100 mV 125 mV Attenuation (%) (2) Loaded media impedance (ohms) Unloaded media impedance (ohms) Terminator bias (mV) Terminator impedance (ohms)
Whenever a requirement for arbitration arises, a SCSI device shall first check to see if its fairness register is clear. If the fairness register is clear, this SCSI device may now participate in arbitration. If the fairness register is not clear, the SCSI device must put off arbitration until all lower priority SCSI IDs have been cleared from the fairness register.
CHAPTER 2 SCSI MESSAGE Message System SCSI Pointer Message Explanation This chapter describes SCSI messages and their operations for controlling the operation sequence of the SCSI bus. Note: The HDD operates as a target device (TARG) on the SCSI bus. The HDD is referred to as the TARG in this chapter except when its clear identification is required.
2.1.2 Message type Message types are shown in Tables 2.1 and 2.2. Function of each message is explained in detail in Section 2.3. Table 2.1 SCSI message Code Number Transfer Message (hex.) of bytes direction release TASK COMPLETE TARG→INIT EXTENDED MESSAGE (See Table TARG↔INIT (See Figure 2.1 and Table 2.2.)
Table 2.2 Extended message Code Number Transfer Message (hex.) of bytes direction release SYNCHRONOUS DATA TRANSFER TARG↔INIT REQUEST WIDE DATA TRANSFER REQUEST TARG↔INIT PARALLEL PROTOCOL REQUEST TARG↔INIT 2.1.3 Message protocol Message implement requirements All SCSI devices shall implement at least the TASK COMPLETE message. If a logical unit number (LUN) for input and output operations is specified in the command (CDB), the minimum I/O operations required on the SCSI bus can be executed without using any message other than the TASK COMPLETE message.
Path establishment of I/O operation After the SELECTION phase, the IDENTIFY, ABORT TASK SET, or TARGET RESET message must first be sent from the INIT to the TARG. The IDENTIFY message can be followed by another message such as a SYNCHRONOUS DATA TRANSFER REQUEST message. If tagged queuing technique is used, the TASK SET message is issued immediately after the IDENTIFY message.
Pointer operation When the TARG issues a request message or executes reconnection, the INIT saves the pointer (that is, the INIT sets the current pointer value to the Saved pointer) or restores the pointer (that is, the INIT sets the Saved pointer value to the current pointer). Within the Saved pointer, the command pointer and status pointer always have their initial value of that command.
Message Explanation This section explains the function of each message. The following symbols are used for message identification. Symbols: (I→T): The message which can be sent from the INIT to the TARG only. (T→I): The message which can be sent from the TARG to the INIT only. (I↔T): The message which can be sent between the INIT and TARG in any direction.
The TARG continues command processing by itself, and reconnects the INIT when necessary (by reconnect processing) to continue command execution on the SCSI bus. This message cannot request the INIT for saving of the current data pointer. Note: To start disconnect processing during data transfer, the TARG must send the SAVE DATA POINTER message for saving of data pointer before sending this message.
• TARGET RESET message: Clear all I/O operations of all INITs existing on all LUNs of the TARG. • CLEAR TASK SET message: Clear all I/O operations of all INITs existing on a specific LUN. • ABORT TASK SET message: Clear all I/O operations of a specific INIT existing on a specific LUN.
2.3.10 LINKED TASK COMPLETE message: X'0A'(T→I) The LINKED TASK COMPLETE message indicates that the link command (with flag bit 0) has been executed normally and that the valid status byte has been posted to the INIT. When the INIT receives this message, it shall update both the current pointer and Saved pointer to the initial values of the next linked command.
2.3.14 CONTINUE TASK message: X'12' (I→T) The CONTINUE TASK message is sent from the INIT to the TARG to reconnect to a task. This message shall be sent as one of the messages within the consecutive message out phases sent after the IDENTIFY message.
When the TARG is ready to transfer data for a disconnected task for which a TARGET TRANSFER DISABLE message has been sent, the TARG shall reconnect to the INIT for the task (via a reselection phase and consecutive message in phases containing an IDENTIFY message, and an optional SIMPLE message), send a DISCONNECT message, and, if the INIT does not respond with a MESSAGE REJECT message, generate a bus free phase.
If the TARG reconnects to the INIT to continue a tagged I/O operation, the TARG sends the SIMPLE message immediately after the IDENTIFY message in the reconnection sequence of the same MESSAGE IN phase. SIMPLE message: X'20'(I↔T) The SIMPLE message specifies that the task be placed in that logical unit's queue. The order of execution is determined by the HDD.
INIT renews the current data pointer according to the invalid number of data bytes notified by this message. Note: The number of effective bytes of data which transfers by the data phase and boundary need not use this message at the data out phase because TARG controls. 2.3.19 IDENTIFY message: X'80' to X'FF' (I↔T) This message specifies the logical unit number (LUN) for the device (logical unit) under the...
If the INIT receives this message in the reconnection sequence, the INIT shall save the Saved pointer value of the specified LUN in the current pointer before completing the current message transfer phase (or before negating the ACK signal). 2.3.20 SYNCHRONOUS DATA TRANSFER REQUEST message (I↔T) Byte X'01'...
When a SCSI device executes data transfer, it must not send REQ or ACK pulses exceeding the parameter limits which have been set by the two SCSI devices by exchange of the SYNCHRONOUS DATA TRANSFER REQUEST message. However, the SCSI device can transfer data using a larger Transfer Period or a smaller REQ/ACK Offset.
mode setting for synchronous transfer between the INIT and the TARG must be set to the asynchronous mode. Procedures of the message exchange initiated by the TARG If the TARG has recognized the synchronous data transfer to be set and if the synchronous data transfer request is enabled by the CHANGE DEFINITION command, the TARG sends the SYNCHRONOUS DATA TRANSFER REQUEST message to the INIT.
The default data transfer mode between SCSI devices is asynchronous data transfer. The asynchronous data transfer mode shall be selected when the power supply is turned on, a TARGET RESET message is received, a RESET condition occurs, or a WIDE DATA TRANSFER REQUEST message is received.
(b) Transfer mode establishment The default transfer mode is released, and the synchronous transfer mode or the asynchronous transfer mode is selected by the exchange of SYNCHRONOUS DATA TRANSFER REQUEST message. This mode is kept for each INIT individually and data transfer mode and synchronous mode parameters of each INIT differ each other.
Table 2.5 Transfer mode setup request from INIT to HDD (SDTR: SYNCHRONOUS DATA TRANSFER REQUEST message) Message from INIT HDD Response Transfer mode to be defined REQ/ACK X'00' SDTR Asynchronous mode Offset REQ/ACK Offset = 0 X'01' SDTR Synchronous mode REQ/ACK Offset REQ/ACK offset <...
d. Transfer mode setup from HDD to INIT When the synchronous data transfer mode is allowed by the CHANGE DEFINITION command, the HDD shall execute one of the following operations if the INIT still continue the default transfer mode. (a) When the ATTENTION condition has been generated: If an ATTENTION condition exists before the COMMAND phase and if the INIT does not send the SYNCHRONOUS DATA TRANSFER REQUEST message after the end of COMMAND phase, the HDD shall try to select the synchronous data transfer mode by...
Table 2.6 Transfer mode setup request from HDD to INIT (SDTR: SYNCHRONOUS DATA TRANSFER REQUEST message) Message from HDD Response from INIT Transfer mode to be defined SDTR MESSAGE REJECT Asynchronous mode REQ/ACK Offset = X'7F' REQ/ACK X'00' Asynchronous mode Offset X'01' Synchronous mode...
2.3.21 WIDE DATA TRANSFER REQUEST message (I↔T) Byte X'01' X'02' X'03' m: Transfer Width Exponent Transfer width = 2 bytes Two SCSI devices exchange the WIDE DATA TRANSFER REQUEST message to determine the data bus width between them. When an SCSI device that supports the wide mode data transfer connects to other SCSI device just after power-on, after the RESET condition occurs, or after it receives the TARGET RESET message, it exchanges this message to determine the wide mode data transfer.
Table 2.7 Data bus width defined by message exchange Response message Data bus width WIDE DATA TRANSFER REQUEST Data is transferred using the responded data bus width. Transfer Width Exponent > 1 WIDE DATA TRANSFER REQUEST 8-bit data transfer Transfer Width Exponent = 0 MESSAGE REJECT message 8-bit data transfer Message exchange started by the INIT...
If the TARG enters the MESSAGE IN phase and first sends the MESSAGE REJECT message to the INIT immediately after the INIT has responded with the WIDE DATA TRANSFER REQUEST message, such message exchange is made invalid and the two SCSI devices shall set the 8-bit data bus width between them.
ended in error, the transfer width between it and the INIT, and the synchronous mode will change to the default transfer mode. Note: When the INIT requests for a change of data bus width, the HDD responds to the request. At this time, the current synchronous transfer mode is reset to the default asynchronous transfer mode.
(b) Without ATTENTION condition If the ATTENTION condition does not exist, the HDD does not send the WIDE DATA TRANSFER REQUEST message to the INIT. In such case, the 8-bit bus width is set between the HDD and the INIT. Table 2.9 Wide mode setting request from the HDD to the INIT Message from TARG...
Table 2.10 TRANSFER PERIOD FACTOR field CODE DESCRIPTION X'00'-X'07' Reserved Transfer period equals 6.25ns (note 2). This code is only valid if the X'08' PROTOCOL OPTIONS field has a value selected that supports precompensation, information units, and double-transition data transfers. Transfer period equals 12.5ns (note 3).
The protocol options bits (PCOMP_EN, RTI, RD_STRM, WR_FLOW, IU_REQ, DT_REQ, QAS_REQ, and HOLD_MCS) are used by the originating SCSI device to indicate the protocol options to be enabled. The responding SCSI device uses the protocol options bits to indicate the protocol options requested by the originating SCSI device the responding SCSI device has enabled.
A DT enable request bit (DT_REQ) of zero indicates that DT DATA phases are to be disabled when received from the originating SCSI device and that DT DATA phases are not supported when received from the responding SCSI device. An DT_REQ bit of one indicates that DT DATA phases are to be enabled when received from the originating SCSI device and that DT DATA phases are supported when received from the responding SCSI device.
A PARALLEL PROTOCOL REQUEST message exchange shall be initiated by a SCSI device whenever a previously arranged parallel protocol agreement may have become invalid. The agreement becomes invalid after any condition that may leave the parallel protocol agreement in an indeterminate state such as: a) RESET condition ("hardware RESET") occurrence b) TARGET RESET message reception c) Power turned off...
Table 2.12 PARALLEL PROTOCOL REQUEST message implied agreement Responding SCSI device PARALLEL Implied agreement PROTOCOL REQUEST response Synchronous transfer (i.e., Each SCSI device transmits data with a period equal to or greater than and a REQ/ACK offset Non-zero REQ/ACK offset equal to or less than the negotiated values received in the responding SCSI device's PPR message).
Following a TARG's responding PARALLEL PROTOCOL REQUEST message, an implied agreement for data transfers shall not be considered to exist until; a) the INIT receives the last byte of the PARALLEL PROTOCOL REQUEST message and parity is valid; and b) the TARG does not detect an attention condition on the last byte of the PARALLEL PROTOCOL REQUEST message.
CHAPTER 3 ERROR RECOVERY Error Conditions and Retry Procedure Recovery Control This chapter describes the SCSI bus errors and their recovery by the HDD. Note: If a severe error has occurred, the HDD may switch the SCSI bus to the BUS FREE phase without sending the DISCONNECT or TASK COMPLETE message to the INIT.
COMMAND phase parity error When the HDD detects a parity error in the COMMAND phase, it retries the Command Phase up to 3 times. If the HDD fails to recover a parity error, it proceeds to the next procedure. If the LUN is already identified by the IDENTIFY message, the HDD terminates the command with the CHECK CONDITION status.
Rejected messages When the HDD receives a MESSAGE REJECT message from the INIT, the HDD executes one of the following depending on the rejected message type: a. TASK COMPLETE The HDD enters the BUS FREE phase immediately, and does not consider this as an error. b.
g. SAVE DATA POINTER When rejecting this message for disconnection of the SCSI bus, the HDD continues the currently executing command without disconnection as the DISCONNECT message is rejected. h. SIMPLE When this message sent next to the IDENTIFY message at reconnection is rejected, the HDD immediately enters the BUS FREE phase and terminates the command which has requested the reconnection abnormally.
The retry count for the timeout of RESELECTION phase can be set by the CHANGE DEFINITION command. For details, see Section 1.6.11. Errors concerning message protocol If the HDD detects an ATTENTION condition in the SELECTION phase and it receives the message except for the following messages from the INIT in its response to the ATTENTION condition (the MESSAGE OUT phase), the HDD considers it as an error in the message protocol and enters the BUS FREE phase immediately.
Recovery Control The HDD performs the error recovery for some kinds of SCSI bus errors (see Section 3.1). All recovery procedures are based on the protocol of SCSI bus phase. Note: If the INIT does not generate an ATTENTION condition, the HDD does not use any message except for the TASK COMPLETE message.
Table 3.1 Retry procedure for SCSI error Termination procedure Error Condition Status Sense data CHECK ABORTED COMMAND Parity error in MESSAGE OUT phase → NO SENSE BUS FREE CHECK ABORTED COMMAND Parity error in COMMAND phase →BUS FREE NO SENSE Parity error in DATA OUT phase CHECK ABORTED COMMAND...
Glossary Bus condition: Asynchronous operation condition used for status transition of SCSI bus. There are two types of bus conditions: ATTENTION and RESET conditions. Bus phase: The name of SCSI bus state. The SCSI bus can be either in the BUS FREE, ARBITRATION, SELECTION, RESELECTION or INFORMATION TRANSFER phase.
Sense data: Detailed information created by the target when any error is involved in the command termination status. This information is transferred to report the error. Sense key: Four-bit code attached to sense data to identify the class of the detected error. Status: One byte of information that is transferred from a target to an initiator on termination of each command to indicate the command termination status.
Abbreviation MeSeaGe ACKnowledge ATenTion American Wire Gauge Original Equipment Manufacturer BuSY Parallel Protocol Request Control/Data REQuest Common Command Set ReSeT Command Descriptor Block SCSI Small Computer System Interface Data Bus SDTR Synchronous Data Transfer Request Data Bus Parity Single-Ended Direct Current SELect Double Transfer Single Transfer...
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