Fujitsu MBA3073 SERIES Technical Manual page 15

Figure 1.34 DT DATA IN phase training pattern ......................................................................................90
Figure 1.35 DT DATA OUT phase training pattern ..................................................................................92
Figure 1.36 Usage of P1 to establish data valid and data invalid states .....................................................93
Figure 1.37 READ STREAM and WRITE FLOW....................................................................................96
Figure 1.38 Data sequence at data transfer.................................................................................................99
Figure 1.39 Data transfer rate in synchronous mode................................................................................101
Figure 1.40 Switching direction of transfer over data bus .......................................................................103
Figure 1.41 ATTENTION condition........................................................................................................107
Figure 1.42 RESET condition ..................................................................................................................109
Figure 1.43 Bus phase sequence (1 of 2) .................................................................................................110
Figure 1.43 Bus phase sequence (2 of 2) .................................................................................................111
Figure 1.44 Example of bus phase transition at execution of a single command (1 of 5)........................112
Figure 1.44 Example of bus phase transition at execution of a single command (2 of 5)........................113
Figure 1.44 Example of bus phase transition at execution of a single command (3 of 5)........................114
Figure 1.44 Example of bus phase transition at execution of a single command (4 of 5)........................115
Figure 1.44 Example of bus phase transition at execution of a single command (5 of 5)........................116
Figure 1.45 Phase sequences for physical reconnection or selection without using attention
condition with information unit transfers enabled ................................................................117
Figure 1.46 Phase sequences for selection with attention condition with information unit
transfers enabled ...................................................................................................................118
Figure 1.47 SPI information unit sequence during initial connection......................................................121
Figure 1.48 SPI information unit sequence during data type transfers ....................................................122
Figure 1.49 SPI information unit sequence during data stream type transfers.........................................123
Figure 1.50 SPI information unit sequence during status transfers..........................................................124
Figure 1.51 State of level-1 SCAM target................................................................................................138
Figure 1.52 State of level-2 SCAM target................................................................................................139
Figure 1.53 Comparison of active negate current and voltage .................................................................144
Figure 1.54 Single-ended test circuit........................................................................................................145
Figure 1.55 LVD transceiver architecture ................................................................................................147
Figure 1.56 Connection to the LVD receivers .........................................................................................148
Figure 1.57 Differential SCSI bus capacitive loading..............................................................................149
Figure 2.1 Message format.....................................................................................................................154
Figure 2.2 SCSI pointer configuration ...................................................................................................159
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