1.6.5.1 Asynchronous Transfer Mode - Fujitsu MBA3073 SERIES Technical Manual

Notes:
1. After the ACK signal becomes false in the current INFORMATION TRANSFER phase,
the TARG can start preparing a new phase by changing the status of C/D, I/O and MSG
signals. The status of these three signals can change in any order or at once. The status
of one signal may change more than once; however, the TARG should change the status
of each signal only once.
2. A new INFORMATION TRANSFER phase starts when the REQ signal requesting to
transfer the first byte in that phase becomes true. The phase ends when one of C/D, I/O
and MSG signals changes after the ACK signal has changed to false. The period after the
end of phase to the start of next phase (which starts when the REQ signal becomes true)
is not defined.
3. The INIT can predict the next new phase (expected phase) by reading the status change
of C/D, I/O or MSG signal or by reading the type of previously executed phase.
However, the expected phase is made valid only when the REQ signal is changed to true.

1.6.5.1 Asynchronous transfer mode

In asynchronous transfer mode, the INIT and TARG control the information transfer by checking
the status change of REQ and ACK signals (between true and false state) by each other (it is
called the interlock control). The asynchronous transfer can be used in all types of
INFORMATION TRANSFER phase (such as COMMAND, DATA, STATUS and MESSAGE).
Figure 1.31 shows the timing of asynchronous transfer.
If the wide mode data transfer is established between the INIT and TARG, the two-byte data
(DB15 to DB0, DBP1, DBP_CRCA) is transferred on the 16-bit SCSI bus. Otherwise, single-
byte data (DB7 to DB0, DBP_CRCA) is transferred.
a. Transfer from TARG to INIT
The TARG determines the information transfer direction by the I/O signal. If the I/O signal is
true, the information of the data bus is transferred from the TARG to the INIT. The following
explains the information transfer sequence.
1) The TARG asserts the REQ signal at least one System Deskew Delay + Cable Skew
Delay after sending valid information on the data bus. It must maintain the state of the
data bus until the ACK signal becomes true on the TARG.
2) The INIT fetches the data from the data bus after the REQ signal becomes true. It asserts
the ACK signal to report the completion of reception.
3) After the ACK signal becomes true on the TARG, the TARG negates the REQ signal and
the TARG may change or release the DB(7-0, P_CRCA) or DB(15-0, P_CRCA, P1)
signals.
4) The INIT negates the ACK signal after the REQ signal becomes false.
5) After the ACK signal becomes false, the TARG proceeds to the next byte transfer stage.
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