Figure 1.19 Transmitter Time Asymmetry - Fujitsu MAW3073 SERIES Specifications

(56) Transmitter time asymmetry
The maximum time on DATA BUS, DB(P1), ACK, or REQ signal from any transition edge to the
subsequent transition edge during a "1010..." pattern, as measured at their zero-crossing points,
minus the data transfer period (see Fig.1-19).
C141-C011

Figure 1.19 Transmitter time asymmetry

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