Fujitsu MAW3073 SERIES Specifications page 68

3) Then the SCSI device that arbitrates the bus asserts the DATA BUS bit corresponding to its
own SCSI ID and BSY signal (*1) within Bus Set Delay after the last observation of the BUS
FREE phase.
4) After waiting at least Arbitration Delay since the SCSI device asserted BSY signal, the SCSI
device shall examine the value on the DATA BUS to determine the priority of the bus
arbitration (*1).
Bus arbitration priority: DB7 (ID#7) > DB6 (ID#6) >... >DB0 (ID#0) >DB15 (ID#15) >DB14
(ID#14) >... >DB8 (ID#8)
•
When the SCSI device detects any ID bit which is assigned higher priority than its own
SCSI ID, the SCSI device shall release its signals (BSY and its SCSI ID) then may return
to step (1).
•
The SCSI device which detects no higher SCSI ID bit on the DATA BUS can obtain the
bus control, then it shall assert SEL signal.
•
Any other SCSI device that is participating in the ARBITRATION phase shall release its
signals within Bus Clear Delay after SEL signal becomes true, then may return to step (1).
5) The SCSI device which wins arbitration shall wait at least Bus Clear Delay + Bus Settle Delay
after asserting SEL signal before changing any signal state.
*1: When an SCSI device sends its SCSI ID to the DATA BUS, it asserts only the bit at the
position corresponding to its own ID and leaves the other or fifteen bits false. The parity bit
(DBP_CRCA or DBP1 signal) may be released or asserted, but must not be actively driven
false. The parity bit on the DATA BUS is unpredictable during an ARBITRATION phase.
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