Fujitsu MAW3073 SERIES Specifications page 77

(2) Response sequence
If a SCSI unit (INIT to be selected) detects the SEL and I/O signals and data bus bit (DBn)
corresponding to the own SCSI ID are all true and if it detects the BSY signal which is false for at
least Bus Settle Delay, the SCSI unit shall recognize that it is selected in the RESELECTION
phase. At this time, the selected INIT samples all bits on the data bus to identify the TARG's SCSI
ID.
The INIT shall respond to the TARG by asserting the BSY signal within Selection Abort Time
from the INIT detects that it is selected.
If the SCSI ID in other than two or bits is detected on the data bus or if a parity error is detected on
the system where the parity bit is enabled on the data bus, the INIT shall not respond to the
RESELECTION phase.
When TARG detects the response (BSY signal) from INIT, the TARG asserts BSY signal and
waits at least Deskew Delay × 2, then the TARG releases SEL signal. At this time, the TARG may
change the I/O signal state and value on the SCSI bus.
The INIT shall release the BSY signal after making sure that the SEL signal becomes false.
The TARG should continue asserting the BSY signal until the TARG relinquishes the SCSI bus.
Note:
When the TARG is asserting the BSY signal, a transmission line phenomenon known as a
wired-OR glitch may cause the BSY signal to appear false for up to a round-trip
propagation delay following the release of the BSY signal by the INIT.
This is the reason why the BUS FREE phase is recognized only after both the BSY and
SEL signals are continuously false for a minimum of one Bus Settle Delay.
C141-C011 1-59