Figure 1.35 Dt Data Out Phase Training Pattern - Fujitsu MAW3073 SERIES Specifications

(3) P1 data valid/invalid state transitions
The transmitting SCSI device port shall indicate the start of a data valid state by reversing the
phase of the P1 signal coincident with a REQ or ACK assertion. This is accomplished by
withholding the next transition of P1 at the start of the first two transfer periods of valid data.
Beginning with the third valid data word, P1 shall be toggled every two transfer periods, coincident
with a REQ or ACK assertion. The minimum duration of the data valid state is two transfer
periods, and the data valid state shall consist of an even number of transfer periods. Anytime the
sending SCSI device port pauses the sending of data, it shall reverse the phase of P1 by
withholding the next transition of P1 at the start of the first two transfer periods that have invalid
data.
Beginning with the third transfer period with invalid data, P1 shall be toggled every two transfer
periods until valid data is sent. The data invalid state shall have at least one transition of P1 before
changing states. The minimum data invalid time is four transfer periods. This ensures a maximum
run length of three cycles for P1. The data invalid state shall last an even number of transfer
periods.
From the data invalid state, the sending SCSI device port may resume sending data by reversing
the phase of P1 again.
P1 has the same transmit setup and hold time requirements as data and shall always be detected by
the receiving device on the assertion edge of the delayed clocked REQ or ACK signal.
See Figure.1.36 for examples of how the P1 signal is used to determine when the REQ or ACK
transition clocks valid data.
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Figure 1.35 DT DATA OUT phase training pattern

C141-C011