General Description - Motorola MVME167 Series User Manual

For minimum RF emissions, it is essential that the conditions above be implemented;
failure to do so could compromise the FCC compliance of the equipment containing
the module.

General Description

The MVME167 is a double-high VMEmodule based on the MC68040 microprocessor.
The MVME167 has 4/8/16/32/64 MB of parity-protected DRAM or
4/8/16/32/64/128/256 MB of ECC-protected DRAM, 8KB of static RAM and time of
day clock (with battery backup), Ethernet transceiver interface, four serial ports with
EIA-232-D interface, four tick timers, watchdog timer, four ROM sockets, SCSI bus
interface with DMA, Centronics printer port, A16/A24/A32/D8/D16/D32/D64
VMEbus master/slave interface, 128KB of static RAM (with optional battery backup),
and VMEbus system controller.
The I/O on the MVME167 is connected to the VMEbus P2 connector. The main board
is connected through a P2 transition board and cables to the transition boards. The
MVME167 supports the transition boards MVME712-12, MVME712-13,
MVME712M, MVME712A, MVME712AM, and MVME712B (referred to in this
manual as MVME712X, unless separately specified). The MVME712X transition
boards provide configuration headers and provide industry standard connectors for the
I/O devices.
The VMEbus interface is provided by an ASIC called the VMEchip2. The VMEchip2
includes two tick timers, a watchdog timer, programmable map decoders for the master
and slave interfaces, and a VMEbus to/from local bus DMA controller, a VMEbus
to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a
VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA transfers to
the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT, or D64/MBLT.
The PCCchip2 ASIC provides two tick timers and the interface to the LAN chip, SCSI
chip, serial port chip, printer port, and BBRAM.
The MEMC040 memory controller ASIC provides the programmable interface for the
parity-protected DRAM mezzanine board.
The MCECC memory controller ASIC provides the programmable interface for the
ECC-protected DRAM mezzanine board.
MVME167/D3
General Description
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