Dma Channel Assignments; Interrupt Assignments; Table B.26:Dma Channel Assignments; B.27 Interrupt Assignments - Advantech AIMB-501 User Manual

B.26

DMA Channel Assignments

Table B.26: DMA Channel Assignments
Channel
0
1
2
3
4
5
6
7
B.27

Interrupt Assignments

Table B.27: Interrupt Assignments
Priority
1
2
3
-
4
5
6
7
8
9
10
11
12
13
14
15
16
B.28

1st MB Memory Map

Table B.28: 1st MB Memory Map
Addr. range (Hex)
E0000h - FFFFFh
CC000h - DFFFFh
C0000h - CBFFFh
A0000h - BFFFFh
00000h - 9FFFFh
Function
Available
Available
Available
ECP Printer Port (LPT1)
Cascade for DMA controller 1
Available
Available
Available
Interrupt# Interrupt source
NMI Parity error detected
IRQ0 Interval timer
IRQ1 Keyboard
IRQ2 Interrupt from controller 2 (cascade)
IRQ8 Real-time clock
IRQ9 Cascaded to INT 0A (IRQ 2)
IRQ10 Serial communication port 3/4/5/6
IRQ11 Serial communication port 7/8/9/10
IRQ12 PS/2 mouse
IRQ13 INT from co-processor
IRQ14 Primary IDE Channel
IRQ15 Secondary IDE Channel
IRQ3 Serial communication port 2
IRQ4 Serial communication port 1
IRQ5 Available
IRQ6 Available
IRQ7 Parallel port 1 (print port)
Device
BIOS
Unused
VGA BIOS
Video Memory
Base memory
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