Motorola MPC821FADS User Manual page 34

Signal Descriptions
Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
60 MODCK1
61 GND
62 RESETA
63
GND
64
65
66 BADDR28
67 GND
68 TEXP
69 GND
70 WAIT_B
71 GND
72 MODCK2
73
GND
74
75
76 —
77
GND
78
79
80 SRESET
81 GND
82 PORST
83 GND
84 HRESET
85 GND
5-20
DAUGHTERBOARD INPUT/
SIGNAL OUTPUT
MODCK1
GND
RESETA
GND
BADDR28
GND
TEXP
GND
WAIT_B
GND
MODCK2
GND
—
GND
SRESET I/O, L, OD Soft Reset signal. This signal is driven by
GND
PORST
GND
HRESET I/O, L, OD Hard Reset signal. This signal is driven by
GND
MPC821FADS-DB USER'S MANUAL
DESCRIPTION
I/O Mode Clock 1 signal. OP2/MODCK1/STS on
the MPC821. Used at power-on reset.
—
I,H Reset signal for PCMCIA port A.
—
I/O,X Burst Address line 28. Dedicated for external
master support. Used to generate a burst
address during external master burst cycles.
Pulled up, but otherwise unused on this board.
—
X,X Timer Expired signal. Not used on this board.
—
I/O, L Wait signal for PCMCIA Slot B. Pulled up, but
otherwise unused on this board.
—
I/O Mode Clock 2 signal. OP3/MODCK2/DSDO on
the MPC821. Used at power-on reset as
MODCK2 and configured afterwards as OP3.
This signal can be configured for another
function.
—
— Not connected.
—
onboard logic and may be driven by offboard
logic with open-drain gate only.
—
X, L Power-On Reset signal. Not used on the
MPC8xxFADS, but generated on the
daughterboard.
—
onboard logic and may be driven by offboard
logic with open-drain gate only.
—
MOTOROLA