Phase Sequence; Signal Delay Times Definition - Fujitsu M3097G Oem Manual

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SELECTION
BUS FREE ARBITRATION
RESELECTION
The signal delay times for each bus phase are defined as follows:
Table 4.4 Signal delay times definition (1/3)
No. Item
1 Arbitration 2.4 os
delay
2 Assertion 90 ns
period
3 Bus Clear 800 ns
delay
4 $ 10
Figure 4.2 Phase sequence
Time
The minimum time an SCSI device shall wait from
asserting BSY for arbitration until the DATA BUS can
be examined to see if arbitration has been won. There is
no maximum time.
The minimum time that a target shall assert REQ (or
REQB) while using synchronous data transfers. Also,
the minimum time that an initiator shall assert ACK
while using synchronous data transfers.
The maximum time for an SCSI device to stop driving all
bus signals after:
(1) The BUS FREE phase is detected (BSY and SEL both
false for a bus settle delay)
(2) SEL is received from another SCSI device during the
ARBITRATION phase
(3) The transition of RST to true.
For the first condition listed, the maximum time for an
SCSI device to clear the bus is 1200 nanoseconds from
BSY and SEL first becoming both false. If an SCSI
device requires more than a bus settle delay to detect
BUS FREE phase, it shall clear the bus within a bus
clear delay minus the excess time.
MESSAGE OUT
COMMAND
DATA IN or
DATA OUT
STATUS
MESSAGE IN
Definition