Supero X7DAE User Manual page 71

Chapter 4: BIOS
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
PCI-E Link Width Workaround
If this feature is set to Enabled, PCI-E Link Width will be degraded to provide a
BIOS workaround solution when an error occurs. The Options are Enabled and
Disabled.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from one
branch to another. Mirror mode allows data correction by maintaining two copies
of data in two branches. Single Channel 0 allows a single DIMM population during
system manufacturing. The options are Interleave, Sequential, Mirroring, and
Single Channel 0.
Branch 0 Rank Sparing/Branch 1 Rank Sparing
Select enable to enable the sparing feature for Branch 0 or Branch 1 of memory
bus. The options are Enabled and Disabled.
Branch 0 Rank Interleaving/Branch 1 Rank Interleaving
Select enable to enable the functions of Memory Interleaving for Branch 0 Rank or
Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
High Bandwidth FSB
Select Enabled to enable high bandwidth FSB support. The options are Enabled
and Disabled.
High Temperature DRAM Operation
When set to Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and Disabled.
4-11