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Resetting the Module
Hardware Reset
Software Reset
Detecting Errors
Chapter 3
A reset signal is provided to initialize the backplane interface circuit and
your own custom-designed circuitry to a known state. Both hardware and
software resets are implemented for your convenience.
The backplane SYSRESET* line drives both the hardware reset
(HRESET*) and the software reset (CRESET*) user access points low (0)
on the breadboard module. HRESET* also goes to the clear input of U13,
which drives all of the control register outputs (access points CR0-CR7)
low (0).
Control register output bit CR0 is used for the software reset. If you write a
"1" to bit CR0, the CRESET* access point on the module is driven low (0)
by U21D. You can use CRESET* any way you choose in your custom
circuitry.
The breadboard module implements the following error/fail circuitry:
The status register implements bit SR2 as a self-test "Passed/Failed"
bit (see Table 2-4). If SR2 (PASSED access point) is set low (0),
indicating your custom circuit self-test either failed or is currently
still executing and the SYSFAIL INHBT bit (CR1 output of the
control register) has been set low (O), then the module sets the
backplane SYSFAIL* line low (true) through U21A and U5D (this is
the default). If either SYSFAIL INHBT or the "PASSED" bit are set
high, SYSFAIL* remains high (false).
The ACFAIL* line has been stubbed onto the module from
backplane connector P1 (pin B3) and is available as a user access
point for your convenience.
BERR* (Buss ERRor). If an invalid bus cycle is discovered, this can
be asserted instead of DTACK*.
Using the HP E1399A 47
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