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User Access Points
Chapter 2
The breadboard module contains traces (stubs) for accessing many of the
signal lines on backplane connector P1. Table 2-13 shows the signal lines
that are brought onto the module but not implemented. They are available as
signal access points for your custom circuits.
Table 2-14 shows all of the implemented signal lines available as access
points, either as inputs from the backplane to your own custom circuitry, or
as outputs to the backplane from your custom circuits.
Table 2-13. User Access Points (Stubs)
Signal Lines
Description
ACFAIL*
AC Input Power failure
BERR*
Bus ERRor signal
SERCLK
Synchronizes data transmission on the VMSbus
SERDAT*
Used for VMSbus data transmission
Table 2-14. User Access Points (Implemented Signals)
A1-A5
Backplane address lines A1-A5 (latched)
BASE+0
ID Register Enable line
Device Type Register Enable line
BASE+2
BASE+4
Status and Control Registers Enable line
BASE+6
User-assignable Enable line
BASE+8
User-assignable Enable line
BASE+A
User-assignable Enable line
BASE+C
User-assignable Enable line
BASE+E
User-assignable Enable line
CR2-CR7
Control Register output lines
DB0-DB15
Breadboard Module internal Data Bus lines
DS0 & DS1
Buffered data strobes
SR0, SR1
Status Register (pulled up)
SR2
Status Register (pulled up)
SR3
Status Register (pulled up)
Status Register (pulled up)
SR4-SR7
DBEN*
Data bus buffer enable
CRESET*
Card RESET, software (CRO) or hardware (SYSRESET*)
Data Transfer ACKnowledge (DTACK high = DTACK* low)
DTACK
DTACK INH
DTACK INHibit
AS
Buffered address strobe
SYSFAIL
Card failure signal (jumpered to GND)
SYSFAIL INH
SYSFAIL INHibit (jumpered to GND)
HRESET*
Hardware RESET (from SYSRESET*)
IRQ
Interrupt ReQuest line, User-implemented jumper to ground
LATCH*
Latches data into write registers
PIACK*
Peripheral Interrupt ACKnowledge line
CADDR
Card ADDRess match
Configuring the HP E1399A 35
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