Dtack, Interrupt, And Control - HP E1399A User Manual

DTACK, Interrupt,
and Control
DTACK
30 Configuring the HP E1399A
Users may connect any or all of these points to custom circuitry, keeping in
mind the pre-defined bit assignments shown in Table 2-2. Data present on
DB0-DB7 would have been written there by the same DTACK state
machine data transfer cycle that provided the LATCH pulse. See "DTACK"
for a discussion of the DTACK state machine operation.
See Chapter 3, "Using the HP E1399A" for additional information on using
the Control Register. Refer to the VXIbus Specification, Section C.2.1.1.2
for detailed information concerning Control Register implementation
restrictions.
An Interface IC (U6) provides the timing and control signals for standard
data transfer cycles and interrupt requests/acknowledgments. Hardware and
software reset signals, together with a card fail signal, have also been
implemented.
The Data Transfer ACKnowledge (DTACK) circuitry is centered around
the Interface IC (U6). A state machine in this IC controls all read and write
data transfer cycles. Operation begins with the state machine in the idle
state. See Figure 2-11 for the following discussion. Table 2-10 lists the parts
for the DTACK circuitry.
Table 2-10. DTACK Circuitry Parts
Reference HP Part Number
Designator
U21C 1820 4643
U6 1820-6731
U5C 1820-4057
U20C,D,F 1820-4242
Figure 2-11. DTACK Circuitry
Description
IC, 74HCT02N Quad 2-input NOR
IC, Interface (PAL)
IC, 74F38N Quad 2-input NAND Buffer
IC, 74HCT14 Hex Schmitt-Trig Invrtr
Chapter 2