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Control
34 Configuring the HP E1399A
Table 2-12 shows the control signals which are implemented (see the
"Backplane Interface Schematic" in Appendix B):
Signal
Definition
AS*
Address strobe, used in data transfer cycles.
DSO*, DS1*
Data strobes, used in the data transfer cycles.
SYSCLK
Provides 16-MHz clock signals to Interface IC (U6) for clocking the
state machines.
SYSFAIL*
SYSFAIL input. If the SYSFAIL INHBT line output of the Control
Register (CR1) is also low (not inhibited), then SYSFAIL* is asserted.
SYSRESET*
System reset signal, normally used to initialize the backplane
interface circuitry (and your own custom circuits) to a known state.
Provides a hardware reset capability. As implemented (HRESET*), it
clears the Status Register and the Control Register. It also asserts
the software reset line (access point CRESET* on the module).
CRESET* can also be asserted via software by writing a high signal
to the Control Register (access point CR0), providing an input to
U21D.
Table 2-12. Control Signals
Chapter 2
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