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24 Configuring the HP E1399A
If a logical address match occurs and IACK* is high (false), equality
detector U18 produces a low at its output which enables U17. Next, equality
detector U17 compares the information on backplane lines A14, A15, AM0,
AM1, and AM3-AM5 to a hardwired code of 11101X01
examined, this hard-wired code will be a match if all three of the following
conditions are true:
a hexadecimal code of either 29
AM0-AM5.
A14 and A15 are both high (1).
LWORD* is high (false).
Either of the two address modifier hexadecimal codes indicated above will
establish A16 addressing per the VXIbus Specification (Section C.2.1.1.4).
In the VXIbus addressing scheme for an A16 device, A14 and A15 are
always set to 1 to select the upper 16K of the 64K A16 address space (per
the VXIbus Specification, Sections A.2.3.3 and C.2.1.1.1). LWORD* is
high (false) when decoding short word transfers.
If a second match occurs at U17, its output goes low. This triggers a data
transfer cycle using the DTACK state machine in the Interface IC (U6) by
the low at U6 input CADDR* (See "DTACK, Interrupt, and Control" for
more information on the DTACK state machine). As part of the data
transfer cycle, U6 sets DBEN* low (true), latching the remaining backplane
address lines (A1-A5) at the U15 outputs to the two 3-to-8-line decoders
(U7 and U8).
Latch U15 ensures that the data is held valid until the data strobes go high
(false) even though the address lines may no longer be valid.
U8 is enabled if G1 is high and both G2A and G2B are low. Therefore, A4
and A5 must both be low to select a register for connection to the data bus
(D0-D15). G1 will be high (via U9C) if there was a match at U17. If U8 is
enabled, backplane lines A1-A3 are decoded to specify which register
(Status, ID, Device Type, or Control) is to be connected to the data bus.
Other user-supplied registers can be selected also. If additional decoding is
necessary, A4 and A5 are accessible on the module. See Table 2-2 and
Figure 2-6, for information on implementing your own register selections.
. Since AM2 is not
2
or 2D
is present on lines
l6
16
Chapter 2
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