Schematic Diagrams
TPM
TPM 1.2
19,34
19,34
19,34
19,34
23
PCLK_TPM
19,34
LPC_FRAME#
4,14,23
PLT_RST#
19,34
SERIRQ
21
PM_CLKRUN#
21
SUS_STAT#
Sheet 57 of 58
TPM
B - 58 TPM
U49
26
LPC_AD0
LAD0
23
LPC_AD1
LAD1
20
LPC_AD2
LAD2
17
LPC_AD3
LAD3
21
TPM
LCLK
22
LFRAME#
16
LRESET#
27
S ERIRQ
15
CLKRUN#
28
LPCPD#
TPM_BADD
9
TESTBI/BADD
7
TPM_PP
P P
1
NC_1
3
NC_2
12
NC_3
8
TESTI
*SLB9635TT
Asserted before entering S3
LPC reset timing:
LPCPD# inactive to LRST# inactive 32~96us
HI: A CCES S
T PM _PP
L OW: NORMA L ( Int er nal P D )
HI: 4E/ 4F H
T PM _BA DD
L OW: 2E/ 2F H
C786
C787
10
VDD1
19
*0.1u_16V_Y5V_04
*0.1u_16V_Y5V_04
VDD2
24
VDD3
3.3VS
5
VSB
C790
*0.1u_16V_Y5V_04
6
GPIO
2
GPIO2
13
X TALI
X TALI
X 15 *ZM 200S_32.768KHZ
14
4
1
X TALO
XTALO
3
2
4
GND_1
11
X 16
*MC-146_32.768KHZ
GND_2
18
4
1
GND_3
25
3
2
GND_4
C791
*18p_50V_NPO_04
P CLK_TPM
R657
*33_04
C793
3.3VS
TP M_PP
R658
*10K_04
TP M_BADD
R659
*10K_04
R660
*10K_04
4,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,29,30,32,33,34,35,36,39,40,43
3.3VS
C788
C789
*0.1u_16V_Y5V_04
*1u_10V_06
C792
*18p_50V_NPO_04
*10p_50V_04
3.3VS
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