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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
List of Pin Functions
Table 10.2 lists the five mobile access interface pin configurations specified by the MSEL pin input level and
communications macro select (MCRS) register (D[1:0]/0x200000).
Pin Name
I/O
Serial IF Ch. 3
MCRS = (0, 0)
DTR
O
DTR
RTS
O
RTS
TXD
O
SOUT3
RI
I
RI
CTS
I
CTS
DCD
I
DCD
DSR
I
DSR
RXD
I
SIN3
CNT1
O
CNT1
CNT2
O
CNT2
GOUT
O
GOUT
Note: Serial IF Ch. 3 requires both MSEL = Low and MCRS = (0, 0).
Basic Settings for Mobile Access Interfaces
Using the mobile access interfaces for communications requires the following basic settings.
Operating Clock
First use the CKD[3:0] bits in the communications block clock frequency divider register (D[3:0]/0x0200004)
to specify the ratio for internally converting the PERICLK clock signal from the CPU core to a lower frequency
(SCK) to conserve power. (See Table 10.3.) Specify the PERICLK frequency and then switch these bits to
produce a frequency between 5 MHz and 10 MHz.
The default setting, after an initial reset, is 1111, which specifies the highest divider (16) for the slowest clock.
CKD3 CKD2 CKD1 CKD0
B-III-10-4
Table 10.2 Mobile Access Interface Pin Configurations
MSEL = Low
UART
communications
MCRS = (0, 0)
DTR
RTS
SOUT
RI
CTS
DCD
DSR
SIN
CNT1
CNT2
GOUT
Table 10.3 Clock Frequency Divider Settings
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
MSEL = High Communications Mode
HDLC
communications
MCRS = (0, 1)
MOPORT2
MOPORT3
TXD
MIPORT0
HDLCLK
–
MIPORT1
RXD
CNT1
CNT2
GOUT
SCK Clock Frequency Divider
Settings
1
fout/16
0
fout/15
1
fout/14
0
fout/13
1
fout/12
0
fout/11
1
fout/10
0
fout/9
1
fout/8
0
fout/7
1
fout/6
0
fout/5
1
fout/4
0
fout/3
1
fout/2
0
fout/2
fout = PERICLK output frequency
EPSON
PDC
communications
communications
MCRS = (1, 0)
MCRS = (1, 1)
MOPORT2
MOPORT2
MOPORT3
MOPORT3
PDCUPD
PHSUPD
MIPORT0
MIPORT0
PDCCLK
PHSCLK
PDCFRM
PHSFRM
MIPORT1
MIPORT1
PDCDWD
PHSDWD
CNT1
CNT1
CNT2
CNT2
GOUT
GOUT
S1C33210 FUNCTION PART
PHS
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