Epson S1C33210 Technical Manual page 180

II CORE BLOCK: BCU (Bus Control Unit)
DRAM random write cycle
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#WE
D[15:0]
DRAM write cycle (fast page or EDO page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; word-write sample
RAS cycle
BCLK
ROW
A[11:0]
#RASx
#HCAS/
#LCAS
#WE
D[15:0]
Figure 4.33 DRAM Word-Write Cycle (fast page or EDO page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian)
RAS cycle
BCLK
ROW
A[11:0]
#RASx
#HCAS
#LCAS
#WE
D[15:8]
D[7:0]
Figure 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode)
B-II-4-28
RAS cycle
ROW
Figure 4.32 2CAS Type DRAM Random Write Cycle
CAS cycle #1
COL #1
write data
CAS cycle #1
Undefined
write data
EPSON
CAS cycle
COL
write data
CAS cycle #2
COL #2
write data
CAS cycle #2
COL
write data
Undefined
Precharge
cycle
Precharge
cycle
Precharge
cycle
S1C33210 FUNCTION PART