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APPENDIX: I/O MAP
Register name
Address
Bit
Areas 12–11
0048124
DF–7
set-up register
(HW)
D6
D5
D4
D3
D2
D1
D0
Areas 10–9
0048126
DF-B
set-up register
(HW)
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Areas 8–7
0048128
DF–9
set-up register
(HW)
D8
D7
D6
D5
D4
D3
D2
D1
D0
B-APPENDIX-24
Name
Function
–
reserved
A12SZ
Areas 12–11 device size selection
A12DF1
Areas 12–11
A12DF0
output disable delay time
–
reserved
A12WT2
Areas 12–11 wait control
A12WT1
A12WT0
–
reserved
A10BW1
Areas 10–9
A10BW0
burst ROM
burst read cycle wait control
A10DRA
Area 10 burst ROM selection
A9DRA
Area 9 burst ROM selection
A10SZ
Areas 10–9 device size selection
A10DF1
Areas 10–9
A10DF0
output disable delay time
–
reserved
A10WT2
Areas 10–9 wait control
A10WT1
A10WT0
–
reserved
A8DRA
Area 8 DRAM selection
A7DRA
Area 7 DRAM selection
A8SZ
Areas 8–7 device size selection
A8DF1
Areas 8–7
A8DF0
output disable delay time
–
reserved
A8WT2
Areas 8–7 wait control
A8WT1
A8WT0
Setting
–
1 8 bits
0 16 bits
A18DF[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
A18WT[2:0]
Wait cycles
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
– –
A10BW[1:0]
Wait cycles
1
1
1
0
0
1
0
0
1 Used
0 Not used
1 Used
0 Not used
1 8 bits
0 16 bits
A10DF[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
A10WT[2:0]
Wait cycles
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
–
1 Used
0 Not used
1 Used
0 Not used
1 8 bits
0 16 bits
A8DF[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
A8WT[2:0]
Wait cycles
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
EPSON
Init. R/W
Remarks
–
–
0 when being read.
0
R/W
1
R/W
3.5
1
2.5
1.5
0.5
–
–
0 when being read.
1
R/W
7
1
6
1
5
4
3
2
1
0
–
–
0 when being read.
3
0
R/W
2
0
1
0
0
R/W
0
R/W
0
R/W
3.5
1
R/W
2.5
1
1.5
0.5
–
–
0 when being read.
7
1
R/W
6
1
5
1
4
3
2
1
0
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
1
R/W
3.5
1
2.5
1.5
0.5
–
–
0 when being read.
1
R/W
7
1
6
1
5
4
3
2
1
0
S1C33210 FUNCTION PART
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