Epson S1C33210 Technical Manual page 419

ABRTIEC: HDLC clear enable bit for Abort (D7) / HDLC clear interrupt enable register (0x0200306)
TXUEIEC: HDLC clear enable bit for Tx underrun/EOM (D6) / HDLC clear interrupt enable register
(0x0200306)
HUNTIEC: HDLC clear enable bit for Hunt(D5) / HDLC clear interrupt enable register (0x0200306)
IDLDIEC: HDLC clear enable bit for idle detect conditions(D4) / HDLC clear interrupt enable register
(0x0200306)
Writing "1" to a bit disables E/S INT interrupts for changes in the corresponding HDLC status bit. Writes of "0" are
ignored. Setting a bit requires writing to the corresponding bit in the HDLC interrupt enable settings register.
Reading this register returns the current setting for these enable bits: disabled ("0") or enabled ("1"). These values are
the same as the corresponding bits in the HDLC interrupt enable settings register.
Writing "1" to ABRTIEC disables E/S INT interrupts when the Abort bit changes in either direction.
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
Writing "1" to TXUEIEC disables E/S INT interrupts when the Tx underrun/EOM bit changes from "0" to "1."
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
Writing "1" to HUNTIEC disables E/S INT interrupts when the Hunt bit changes from "0" to "1."
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
Writing "1" to IDLDIEC disables E/S INT interrupts when the idle detect bit changes from "0" to "1."
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
EPSON
B-III-10-33