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V DMA BLOCK: HSDMA (High-Speed DMA)
IOC16–IOC15: P1[6:5] port I/O control (D[6:5]) / P1 I/O control register (0x402D6)
Direct the I/O port for input or output.
Write "1": Output mode
Write "0": Input mode
Read: Valid
To use the #DMAEND0 pin (channel 0), direct the pin for output by writing "1" to IOC15; to use the #DMAEND1
pin (channel 1), direct the pin for output by writing "1" to IOC16. If these pins are set for input, the P15 and P16 pins
do not function as the #DMAENDx output pins even when CFP15 and CFP16 are set to "1".
At cold start, IOC1x is set to "0" (input mode). At hot start, IOC1x retains the previous state before an initial reset.
CFP33–CFP32: P3[3:2] pin function selection (D[3:2]) / P3 function select register (0x402DC)
Set the #DMAACKx pin of HSDMA.
Write "1": #DMAACKx output
Write "0": I/O port
Read: Valid
When using the #DMAACK0 signal, set the P32 pin for the #DMAACK0 output pin by writing "1" to CFP32.
Similarly, when using the #DMAACK1 signal, set the P33 pin for the #DMAACK1 output pin by writing "1" to
CFP33.
If CFP3x is set to "0", the pin is set for an I/O port.
At cold start, CFP3x is set to "0" (I/O port). At hot start, CFP3x retains the previous status before an initial reset.
CFEX7–CFEX4: P0[7:4] pin function extension (D[7:4]) / Port function extension register (0x402DF)
Set the port function.
Write "0": I/O-port/serial interface I/O
Read: Valid
Always write "0" to CFEX4 and CFEX5.
When CFEXx is set to "0", the corresponding CFP bit becomes effective.
At cold start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous
status before an initial reset.
B-V-2-28
EPSON
S1C33210 FUNCTION PART
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