E05A02La Gate Array - Epson LQ-1050 Technical Manual

REV.-A

2.3.10.1 E05A02LA Gate Array

The E05A02LA Gate Array includes circuits to interface the CPU and printhead. This general purpose
gate array has special commands that lighten the load on the CPU when outputting printhead data.
Figure 2-74 is a block diagram of the E05A02LA gate array. The gate array mainly consists
latches: 8 bits X 3 = 24 bits. The gate array has functins (commands) for writing data to all
of the data latches efficiently.
DO- 0 7
ADDRESS
DECODE
A O —
DATA LATCH
I
I
I
HPW
1 1
DIR
3'RD
BYTE
LATCH
CLOCK CONTROL
FOR
DATA LATCH
AND COUNTER
TRIPLE
COUNTER
Fig. 2-74. E05A02LA Block Diagram
R
I
:LK
—
I
2-70
DATA LATCH
BLOCK I
DATA LATCH
BLOCK 2
DATA LATCH
BLOCK 3
of data
24 bits
H 1?
H24