Epson LQ-1050 Technical Manual page 112

Because the ~ terminal of this gate array is activated by accessing address FD2 X H, the command
output address and data output address are determined as shown in Table 2-28.
1/0 Address
Outputs a command:
Bit 7: Data latch writing sequence setup
Bit 6: HPW valid/invalid setting
Bit 5: Counter resetting
Bit 4
Bit O
Laches data and increases the counter: "–
When latching data, the data is NANDed with the contents of the current latch and
is protected against double writes (the same data cannot be output twice in
succession).
Latching data into all the data latches is completed by latching three bytes, one at
a time.
The REDY output goes high upon receiving the ~ signal that latches the third byte,
and further data transfer is automatically inhibited.
When ~ is valid as a command, the latched head data is inverted, then is output
while HPW is low.
The REDY output goes low at the leading edge of HPW and informs the CPU that
the gate array can accept more data.
NOTE:
When HPW is set invalid, the HPW output will be in the open-drain ON state independent of
the HPW input. The drive pulse is input to the HPW terminal.
Figure 2-75 also shows the E05A02LA initialization sequence.
Table 2-28. E05A02LA Gate Array Functions
O: Ascending order
1: Dscending order
Optional
J
Function
2-71
REV.-A