Hpw Trigger Pulse Generation Circuit - Epson LQ-1050 Technical Manual

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2.3.10.2 HPW Trigger Pulse Generation Circuit

Figure 2-76 shows the HPW trigger pulse generation circuit. Figure 2-77 and Table 2-29 show the state
and time of each terminal respectively. This circuit employs a 555 timer IC (7C) as a monostable
oscillator. When the PC6 (pin 23) pulse from the CPU is applied to the trigger terminal (pin 2), the duty
cycle of the reference trigger pulse is determined by time constant T, which is controlled by PC5 from
the CPU. When output Q (pin 3) goes high and capacitor C31 is charged to 2/3 Vcc (about 3.2 V), TH
(pin 6) turns on and Q goes low. At that time, C31 is discharged through DIS (pin 7). Every time a pulse
is applied to Trg, the sequence described above is repeated. The HPW low time is controlled (head
trigger pulse width control) by switching PC5 on and off. Figure 2-78 lists is relationship.
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CPU
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# 9- 16
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Fig. 2-75. E05A02LA
+35
Fig. 2-76. HPW Trigger Pulse Generation Circuit
3
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I n i t i a l i z e o r
Initialize Sequence
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5
4,75
2 4
8 ~rg R
555 '
C34 : :
Q
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2-72
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DATA x 3
Pr in 1 i ng
MMU (IOC)
6
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C35
R9
DATA 3
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