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G3 FACSIMILE COMMUNICATIONS
with transmission speeds exceeding 9600 bps were developed. Due to this
background, ITU-T decided in 1985 on the standardization of a 14400 bps
MODEM that used a coding QAM method as a MODEM exclusively for
4-wire exclusive lines. Then in 1988, this MODEM was officially recom-
mended as V.33, and facsimiles that were capable of communicating with
MODEMs made by other companies and that were capable of 14400 bps
communications using proprietary modes were developed as MODEMs
compliant with this recommendation. Then in 1991, a MODEM compliant
with recommendation V.17 that was recommended officially by ITU-T as a
2-wire MODEM for facsimiles was developed. Recently, V.33 MODEMs
are no longer used, and V.17 MODEMs that demonstrate excellent com-
municability with facsimiles made by other manufacturers have gained in
popularity as MODEMs for facsimiles having transmission speeds in
excess of 9600 bps.
The following describes trellis coding/Vitterbi decoding of error correction
coding scheme that are currently used on V.17 MODEMs.
5.5.1 Basic principles of trellis coding and vitterbi decoding
Much research into error correction coding has been conducted since 30 to
40 years ago. This all began with Shannon in 1948 who announced that an
error correction code capable of reducing the error rate exists after decod-
ing is performed on a communications path that contains noise. Of the
numerous error coding schemes, trellis coding and Vitterbi decoding that
are currently used in V.17 MODEMs are suited to correction of random
errors, and are known as error correction coding schemes that obtain
extremely efficient coding gain. Vitterbi decoding was announced in 1967
by Vitterbi as a decoding method for trellis coding (also called "convolu-
tional coding").
(1) Trellis coding
Fig. 5-49 shows a basic convolutional coder. This convolutional coder
comprises a two-stage shift register. Continuous input data is input to this
shift register one bit at a time. Two bits of data are output at each input of
one bit. Output data comprises data ([1] in figure) obtained by taking the
sum of the input data and
bits before that are currently stored to the shift register, and data ([2] in fig-
ure) obtained by taking the sum of the input data and modulo 2 of the input
data two bits before that is currently stored to the shift register. In other
words, the coding ratio is 1/2 as this coder outputs 2-bit coded data for one
bit of input data. The length of input data that participates with output of
5–56
modulo 2
of the input data one bit before and two
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