Acer Extensa 61X Service Manual page 79

Table 2-3 M1523 Signal Descriptions (continued)
Signal
Miscellaneous
MSCLK
RTC32KI
RTC32KII
SIRQI
SIRQII/IRQ8J
USBCLK
USBP1[1:0]
Power Management
EXTSW /
APICREQJ
SMIJ / APICCSJ
STPCLKJ /
APICGNTJ
IDE Interface
IDRQ[1:0]
IDAKJ[1:0]
IDERDY
IDEIORJ
IDEIOWJ
IDESCS1J
IDESCS3J
IDEPCS1J
IDEPCS3J
IDE_A[2:0]
2-22
Pin Type
154 O
16 I
15 I
44 I
45 I
46 I
59, 60 I/O
61 I
50 O
51 O
138-137 I
143-142 O
141 I
140 O
139 O
149 O
150 O
147 O
148 O
145, 144, 146 O
Description
Mouse Clock Output when the internal KBC is enabled.
RTC 32.768K Osc1. This is crystal input and requires an
external 32.768khz quartz crystal.
RTC 32.768K Osc2. This is crystal input and requires an
external 32.768khz quartz crystal.
Steerable IRQ Input 1
Steerable IRQ Input 2 when the internal RTC is enabled.
RTC interrupt input when the internal RTC is disabled.
Universal serial bus clock pin (reserved).
Universal serial bus data pin (reserved).
External SMI Switch or APIC Request Input. EXTSW is a
falling edge triggered input to the M1523 showing that an
external device is requesting the system to enter SMM
mode. An external pull-up should be placed on this signal
if it is not used or it is not guaranteed to be always driven.
When external APIC mode is enabled, this pin is
APICREQJ.
SMM Interrupt or APIC Chip Select.
output asserted by the M1523 in response to one of many
enabled hardware or software events. When external APIC
mode is enabled, this pin is APICCSJ.
Stop CPU Clock Request or APIC Grant Output.
STPCLKJ is connected directly to the CPU and is
synchronous with PCI clock. When external APIC mode is
enabled, this pin is APICGNTJ.
IDE DRQ Request for IDE Master
IDE DACKJ for IDE Master
IDE Ready
IDE IORJ Command
IDE IOWJ Command
IDE chip Select for Secondary Channel 0
IDE chip Select for Secondary Channel 1
IDE chip Select for Primary Channel 0
IDE chip Select for Primary Channel 1
IDE ATA Address Bus
A synchronous
Service Guide