Acer Extensa 61X Service Manual page 68

Table 2-2 M1521 Signal Descriptions (continued)
Signal
Secondary Cache Interface
CCSJ/CB4 W16
GWEJ Y16
COEJ U15
BWEJ/CGCSJ Y17
TIO[10]/ Y20
MWEJ[1]
TIO[9]/ Y19
SRASJ[1]
TIO[8]/ W19
SCASJ[1]
TIO[7:0] Y18, W18, V18, T14,
V17, U17, U16, P16
TWEJ V16
PCI Interface
AD[31:28] A2, B2, A3, B3, A4, B4,
AD[27:24] C4, D6, B5, C5, A6, B6,
AD[23:20] C6, A7, B7, C7, C8, A9,
AD[19:16] B9, C9, A10, B10, C10,
AD[15:12] A11, C11, A12, B12,
AD[11:08] C12, A13, B13, A14,
AD[07:04] A15
AD[03:00]
CBEJ[3:0] A5, A8, B8, B11
FRAMEJ E6
DEVSELJ E9
IRDYJ E7
Major Chips Description
Pin Type
O
O
O
O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
Description
Synchronous SRAM chip select or Cache Address
line 4 copy. This pin has two modes of operation
depending on the type of SRAM selected via
hardware strapping options or programming the CC
register.
Synchronous SRAM
Asynchronous SRAM Write Enable.
Synchronous/Asynchronous SRAM Output Enable.
Synchronous SRAM
Asynchronous SRAM Global Chip Select.
SRAM Tag[10] or another copy of MWEJ.
SRAM Tag[9] or synchronous DRAM (SDRAM) RAS
copy 1.
SRAM Tag[8] or synchronous DRAM (SDRAM) CAS
copy 1.
SRAM Tag[7:0]. This pin contains the L2 tag
address for 256 KB L2 caches. TIO[6:0] contain the
L2 tag address and TIO7 contains the L2 cache valid
bit for 512 KB caches.
Tag Write Enable.
writes into the external tag new state and tag
addresses.
PCI Address-and-Data Bus Lines.
connect to the PCI bus. AD[31:0] contain the
information of address or data for PCI transactions.
PCI Bus Command and Byte Enables.
commands and byte enables are multiplexed in
these lines for address
respectively.
Cycle Frame of PCI Buses.
beginning and duration of a PCI access.
Device Select. When the target device has decoded
the address as its own cycle, it asserts DEVSELJ.
Initiator Ready. This indicates the initiator is ready
to complete the current data phase of transaction.
Global Write Enable
Byte-Write Enable/
This signal, when asserted,
These lines
and data phases,
This indicates the
or
Bus
2-11