Acer Extensa 61X Service Manual page 101

Table 2-10 C&T 65550 Pin Descriptions (continued)
Pin# Pin Name
CPU Direct / VL-Bus Interface (continued)
43 BE0# (BLE#)
32 BE1#
21 BE2#
10 BE3#
179 A2
180 A3
182 A4
183 A5
185 A6
186 A7
187 A8
188 A9
189 A10
190 A11
191 A12
192 A13
193 A14
194 A15
195 A16
196 A17
197 A18
189 A19
199 A20
200 A21
201 A22
28 A23
29 A24
30 A25
53 A26
54 A27
2-44
Type
In Byte Enable 0. Indicates data transfer on D7:D0 for the
current cycle.
In Byte Enable 1. Indicates data transfer on D15:D8 for the
current cycle.
In Byte Enable 2. Indicates data transfer on D23:D16 for the
current cycle.
In Byte Enable 3. BE3# indicates that data will transfer over the
data bus on D31 :24 during the current access.
In System Address Bus. In VL-Bus, and direct CPU interfaces,
In the address pins are connected directly to the bus. In internal
In clock synthesizer test mode (TS# = 0 at Reset), A24
In becomes VCLK out and A25 becomes MCLK out. A26 and
In A27 may be alternately used as General Purpose I/O pins or
In as Activity Indicator and Enable Backlight respectively (see
In panel interface pin descriptions, and FROF and FROC for
In more details). If A26 and A27, are used as GPIO pins, they
In may be programmed as a 2-pin CRT Monitor DDC interface
In (VESA™ "Display Data Channel" also referred to as the
In "Monitor Plug-n-Play" interface). Either A26 or A27 may also
In be used to output, Composite Sync for support of an external
In NTSC / PAL encoder chip.
In
In
In
In
In
In
In
In
In
In
In
In
In
Description
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