Acer Extensa 61X Service Manual page 69

Table 2-2 M1521 Signal Descriptions (continued)
Signal
TRDYJ E8
STOPJ E11
LOCKJ E5
REQJ[3:0] D13, D11, D9, D7
GNTJ[3:0] D14, D12, D10, D8
PHLDJ D4
PHLDAJ D5
PAR E12
SERRJ E13
Clock, Reset, and Suspend Interfaces
RSTJ T15
SUSPENDJ P6
HCLKIN K16
PCLKIN E10
32K W17
UMA Interface
MREQJ/ H6
REQJ[4]
2-12
Pin Type
I/O
I/O
I/O
I
O
I
O
I/O
O
I
I
I
I
I
I
Description
Target Ready. This indicates the target is ready to
complete the current data phase of transaction.
Stop. This indicates the target is requesting the
master to stop the current transaction.
Lock Resource Signal.
master or the bridge intends to do exclusive
transfers.
Bus request signals of PCI Masters. When asserted,
it means the PCI master is requesting the PCI bus
ownership from the arbiter.
Grant signals to PCI Masters. When asserted by the
arbiter, it means the PCI master has been legally
granted to own the bus.
PCI bus hold request. This active low signal is a
request from M1523 for the PCI bus.
PCI bus hold acknowledge. This active low signal
grants PCI to M1523.
Parity bit of PCI buses.
across PAD[31:0] and CBEJ[3:0].
System Error. If the M1521 detects parity errors in
DRAMs, it asserts SERRJ to notify the system.
System Reset. This pin, when asserted, resets the
M1521 and sets the register bits to their default
values.
Suspend. When actively sampled, the M1521 enters
the I/O suspend mode. This signal should be pulled
high when the suspend feature is disabled.
CPU Bus Clock Input. This signal is used by all of
the M1521 logic that is in the host clock domain.
PCI Bus Clock Input. This signal is used by all of
the M1521 logic that is in the PCI clock domain.
The refresh reference clock of frequency 32khz
during suspend mode. This signal should be pulled
to a fixed value when the suspend feature is
disabled.
Memory Request. This input signal is from the GUI
device's MREQJ output. This pin can also be used
as bus request signal of the fifth PCI master.
This indicates the PCI
It is the even parity bit
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