Post Checkpoint List - Acer Extensa 61X Service Manual

BIOS POST Checkpoints
This appendix lists the POST checkpoints of the notebook BIOS.
Table E-1

POST Checkpoint List

Checkpoint
04h
08h
09h
0Ah
0Bh
10h
14h
18h
1Ch
1Dh, 1Eh
BIOS POST Checkpoints
Check CPU ID
Dispatch Shutdown Path
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to
determine whether this POST is caused by a cold or warm boot. If it is a cold
boot, a complete POST is performed. If it is a warm boot, the chip initialization
and memory test is eliminated from the POST routine.
Reset PIE, AIE, UIE
Note: These interrupts are disabled in order to avoid any incorrect actions from
happening during the POST routine.
Initialize m1511
Initialize m1513
Initialize m7101
DMA(8237) testing & initialization
System Timer(8254) testing & initialization
DRAM refresh cycle testing
Set default SS:SP= 0:400
CMOS shutdown byte test, battery, and check sum
Note: Several parts of the POST routine require the system to be in protected
mode. When returning to real mode from protected mode, the processor is
reset, therefore POST is re-entered. In order to prevent re-initialization of the
system, POST reads the shutdown code stored in location 0Fh in CMOS
RAM. Then it jumps around the initialization procedure to the appropriate
entry point.
The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to
execute POST properly.
Initialize default CMOS setting if CMOS bad
Initialize RTC time base
Note: The RTC has an embedded oscillator that generates 32.768 KHz frequency.
To initialize the RTC time base, turn on this oscillator and set a divisor to
32768 so that the RTC can count time correctly
DRAM type determination
A p p e n d A p p e n d i x
Description
i x E E
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